mirror of
https://github.com/yuri91/ili9341-rs.git
synced 2024-11-21 22:30:59 +00:00
cargo fmt
This commit is contained in:
Yuri Iozzelli
parent
651aba971b
commit
799dc143b8
2 changed files with 112 additions and 110 deletions
192
src/gpio.rs
192
src/gpio.rs
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@ -3,120 +3,120 @@ use embedded_hal::digital::v2::OutputPin;
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/// `Interface` implementation for GPIO interfaces
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pub struct Gpio8Interface<'a, DATA, CSX, WRX, RDX, DCX> {
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data_pins: &'a mut [DATA; 8],
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csx: CSX,
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wrx: WRX,
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rdx: RDX,
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dcx: DCX,
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data_pins: &'a mut [DATA; 8],
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csx: CSX,
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wrx: WRX,
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rdx: RDX,
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dcx: DCX,
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}
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impl<'a, CSX, WRX, RDX, DCX, PinE>
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Gpio8Interface<'_, &'a mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
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Gpio8Interface<'_, &'a mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
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where
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CSX: OutputPin<Error = PinE>,
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WRX: OutputPin<Error = PinE>,
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RDX: OutputPin<Error = PinE>,
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DCX: OutputPin<Error = PinE>,
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CSX: OutputPin<Error = PinE>,
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WRX: OutputPin<Error = PinE>,
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RDX: OutputPin<Error = PinE>,
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DCX: OutputPin<Error = PinE>,
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{
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/// Create a new Gpio8Interface
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///
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/// Example useage:
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///
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/// let csx = gpioc.pc2.into_push_pull_output();
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/// let wrx = gpiod.pd13.into_push_pull_output();
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/// let rdx = gpiod.pd12.into_push_pull_output();
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/// let dcx = gpiof.pf7.into_push_pull_output();
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///
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/// let mut data_pins: [&mut dyn OutputPin<Error = _>; 8] = [
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/// &mut gpiod.pd6.into_push_pull_output(),
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/// &mut gpiog.pg11.into_push_pull_output(),
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/// ...
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/// ];
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///
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/// let if_gpio = ili9341::gpio::Gpio8Interface::new(&mut data_pins, csx, wrx, rdx, dcx);
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pub fn new(
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data_pins: &'a mut [&'a mut dyn OutputPin<Error = PinE>; 8],
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csx: CSX,
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wrx: WRX,
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rdx: RDX,
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dcx: DCX,
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) -> Self {
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Self {
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data_pins,
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csx,
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wrx,
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rdx,
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dcx,
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}
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}
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/// Create a new Gpio8Interface
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///
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/// Example useage:
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///
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/// let csx = gpioc.pc2.into_push_pull_output();
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/// let wrx = gpiod.pd13.into_push_pull_output();
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/// let rdx = gpiod.pd12.into_push_pull_output();
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/// let dcx = gpiof.pf7.into_push_pull_output();
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///
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/// let mut data_pins: [&mut dyn OutputPin<Error = _>; 8] = [
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/// &mut gpiod.pd6.into_push_pull_output(),
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/// &mut gpiog.pg11.into_push_pull_output(),
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/// ...
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/// ];
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///
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/// let if_gpio = ili9341::gpio::Gpio8Interface::new(&mut data_pins, csx, wrx, rdx, dcx);
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pub fn new(
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data_pins: &'a mut [&'a mut dyn OutputPin<Error = PinE>; 8],
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csx: CSX,
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wrx: WRX,
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rdx: RDX,
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dcx: DCX,
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) -> Self {
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Self {
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data_pins,
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csx,
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wrx,
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rdx,
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dcx,
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}
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}
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/// Sets the gpio data pins used in the parallel interface
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fn set_data_bus(&mut self, data: u8) -> Result<(), Error<PinE, PinE>> {
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for (i, d) in self.data_pins.iter_mut().enumerate() {
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if ((data >> i) & 0b1) == 0b1 {
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d.set_high().map_err(Error::OutputPin)?;
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} else {
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d.set_low().map_err(Error::OutputPin)?;
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}
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}
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Ok(())
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}
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/// Sets the gpio data pins used in the parallel interface
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fn set_data_bus(&mut self, data: u8) -> Result<(), Error<PinE, PinE>> {
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for (i, d) in self.data_pins.iter_mut().enumerate() {
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if ((data >> i) & 0b1) == 0b1 {
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d.set_high().map_err(Error::OutputPin)?;
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} else {
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d.set_low().map_err(Error::OutputPin)?;
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}
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}
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Ok(())
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}
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}
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impl<'a, CSX, WRX, RDX, DCX, PinE> Interface
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for Gpio8Interface<'_, &mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
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for Gpio8Interface<'_, &mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
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where
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CSX: OutputPin<Error = PinE>,
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WRX: OutputPin<Error = PinE>,
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RDX: OutputPin<Error = PinE>,
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DCX: OutputPin<Error = PinE>,
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CSX: OutputPin<Error = PinE>,
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WRX: OutputPin<Error = PinE>,
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RDX: OutputPin<Error = PinE>,
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DCX: OutputPin<Error = PinE>,
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{
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type Error = Error<PinE, PinE>;
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type Error = Error<PinE, PinE>;
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fn write(&mut self, command: u8, data: &[u8]) -> Result<(), Self::Error> {
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self.csx.set_low().map_err(Error::OutputPin)?;
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self.rdx.set_high().map_err(Error::OutputPin)?;
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self.dcx.set_low().map_err(Error::OutputPin)?;
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self.wrx.set_low().map_err(Error::OutputPin)?;
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fn write(&mut self, command: u8, data: &[u8]) -> Result<(), Self::Error> {
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self.csx.set_low().map_err(Error::OutputPin)?;
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self.rdx.set_high().map_err(Error::OutputPin)?;
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self.dcx.set_low().map_err(Error::OutputPin)?;
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self.wrx.set_low().map_err(Error::OutputPin)?;
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self.set_data_bus(command)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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self.set_data_bus(command)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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self.dcx.set_high().map_err(Error::OutputPin)?;
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for val in data.iter() {
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self.wrx.set_low().map_err(Error::OutputPin)?;
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self.set_data_bus(*val)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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}
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self.dcx.set_high().map_err(Error::OutputPin)?;
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for val in data.iter() {
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self.wrx.set_low().map_err(Error::OutputPin)?;
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self.set_data_bus(*val)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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}
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self.csx.set_high().map_err(Error::OutputPin)?;
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self.csx.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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Ok(())
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}
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fn write_iter(
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&mut self,
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command: u8,
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data: impl IntoIterator<Item = u16>,
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) -> Result<(), Self::Error> {
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self.csx.set_low().map_err(Error::OutputPin)?;
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self.rdx.set_high().map_err(Error::OutputPin)?;
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self.dcx.set_low().map_err(Error::OutputPin)?;
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self.wrx.set_low().map_err(Error::OutputPin)?;
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fn write_iter(
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&mut self,
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command: u8,
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data: impl IntoIterator<Item = u16>,
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) -> Result<(), Self::Error> {
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self.csx.set_low().map_err(Error::OutputPin)?;
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self.rdx.set_high().map_err(Error::OutputPin)?;
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self.dcx.set_low().map_err(Error::OutputPin)?;
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self.wrx.set_low().map_err(Error::OutputPin)?;
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self.set_data_bus(command)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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self.set_data_bus(command)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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self.dcx.set_high().map_err(Error::OutputPin)?;
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for val in data.into_iter() {
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for b in &val.to_be_bytes() {
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self.wrx.set_low().map_err(Error::OutputPin)?;
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self.set_data_bus(*b)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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}
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}
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self.dcx.set_high().map_err(Error::OutputPin)?;
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for val in data.into_iter() {
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for b in &val.to_be_bytes() {
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self.wrx.set_low().map_err(Error::OutputPin)?;
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self.set_data_bus(*b)?;
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self.wrx.set_high().map_err(Error::OutputPin)?;
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}
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}
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self.csx.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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self.csx.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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}
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30
src/spi.rs
30
src/spi.rs
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@ -1,7 +1,7 @@
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use crate::{Error, Interface};
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use embedded_hal::blocking::spi;
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use embedded_hal::spi::{Mode, Phase, Polarity};
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use embedded_hal::digital::v2::OutputPin;
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use crate::{Interface, Error};
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use embedded_hal::spi::{Mode, Phase, Polarity};
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/// SPI mode
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pub const MODE: Mode = Mode {
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@ -17,23 +17,21 @@ pub struct SpiInterface<SPI, CS, DC> {
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}
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impl<SPI, CS, DC, SpiE, PinE> SpiInterface<SPI, CS, DC>
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where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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where
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SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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{
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pub fn new(spi: SPI, cs: CS, dc: DC) -> Self {
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Self {
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spi,
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cs,
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dc,
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}
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Self { spi, cs, dc }
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}
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}
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impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC>
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where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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where
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SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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{
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type Error = Error<SpiE, PinE>;
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@ -50,7 +48,11 @@ impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC>
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Ok(())
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}
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fn write_iter(&mut self, command: u8, data: impl IntoIterator<Item=u16>) -> Result<(), Self::Error> {
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fn write_iter(
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&mut self,
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command: u8,
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data: impl IntoIterator<Item = u16>,
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) -> Result<(), Self::Error> {
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self.cs.set_low().map_err(Error::OutputPin)?;
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self.dc.set_low().map_err(Error::OutputPin)?;
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