diff --git a/src/gpio.rs b/src/gpio.rs
index f6c310b..1c59920 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -3,120 +3,120 @@ use embedded_hal::digital::v2::OutputPin;
 
 /// `Interface` implementation for GPIO interfaces
 pub struct Gpio8Interface<'a, DATA, CSX, WRX, RDX, DCX> {
-	data_pins: &'a mut [DATA; 8],
-	csx: CSX,
-	wrx: WRX,
-	rdx: RDX,
-	dcx: DCX,
+    data_pins: &'a mut [DATA; 8],
+    csx: CSX,
+    wrx: WRX,
+    rdx: RDX,
+    dcx: DCX,
 }
 
 impl<'a, CSX, WRX, RDX, DCX, PinE>
-	Gpio8Interface<'_, &'a mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
+    Gpio8Interface<'_, &'a mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
 where
-	CSX: OutputPin<Error = PinE>,
-	WRX: OutputPin<Error = PinE>,
-	RDX: OutputPin<Error = PinE>,
-	DCX: OutputPin<Error = PinE>,
+    CSX: OutputPin<Error = PinE>,
+    WRX: OutputPin<Error = PinE>,
+    RDX: OutputPin<Error = PinE>,
+    DCX: OutputPin<Error = PinE>,
 {
-	/// Create a new Gpio8Interface
-	///
-	/// Example useage:
-	///
-	/// let csx = gpioc.pc2.into_push_pull_output();
-	/// let wrx = gpiod.pd13.into_push_pull_output();
-	/// let rdx = gpiod.pd12.into_push_pull_output();
-	/// let dcx = gpiof.pf7.into_push_pull_output();
-	///
-	/// let mut data_pins: [&mut dyn OutputPin<Error = _>; 8] = [
-	/// 	&mut gpiod.pd6.into_push_pull_output(),
-	/// 	&mut gpiog.pg11.into_push_pull_output(),
-	/// 	...
-	/// ];
-	///
-	/// let if_gpio = ili9341::gpio::Gpio8Interface::new(&mut data_pins, csx, wrx, rdx, dcx);
-	pub fn new(
-		data_pins: &'a mut [&'a mut dyn OutputPin<Error = PinE>; 8],
-		csx: CSX,
-		wrx: WRX,
-		rdx: RDX,
-		dcx: DCX,
-	) -> Self {
-		Self {
-			data_pins,
-			csx,
-			wrx,
-			rdx,
-			dcx,
-		}
-	}
+    /// Create a new Gpio8Interface
+    ///
+    /// Example useage:
+    ///
+    /// let csx = gpioc.pc2.into_push_pull_output();
+    /// let wrx = gpiod.pd13.into_push_pull_output();
+    /// let rdx = gpiod.pd12.into_push_pull_output();
+    /// let dcx = gpiof.pf7.into_push_pull_output();
+    ///
+    /// let mut data_pins: [&mut dyn OutputPin<Error = _>; 8] = [
+    ///     &mut gpiod.pd6.into_push_pull_output(),
+    ///     &mut gpiog.pg11.into_push_pull_output(),
+    ///     ...
+    /// ];
+    ///
+    /// let if_gpio = ili9341::gpio::Gpio8Interface::new(&mut data_pins, csx, wrx, rdx, dcx);
+    pub fn new(
+        data_pins: &'a mut [&'a mut dyn OutputPin<Error = PinE>; 8],
+        csx: CSX,
+        wrx: WRX,
+        rdx: RDX,
+        dcx: DCX,
+    ) -> Self {
+        Self {
+            data_pins,
+            csx,
+            wrx,
+            rdx,
+            dcx,
+        }
+    }
 
-	/// Sets the gpio data pins used in the parallel interface
-	fn set_data_bus(&mut self, data: u8) -> Result<(), Error<PinE, PinE>> {
-		for (i, d) in self.data_pins.iter_mut().enumerate() {
-			if ((data >> i) & 0b1) == 0b1 {
-				d.set_high().map_err(Error::OutputPin)?;
-			} else {
-				d.set_low().map_err(Error::OutputPin)?;
-			}
-		}
-		Ok(())
-	}
+    /// Sets the gpio data pins used in the parallel interface
+    fn set_data_bus(&mut self, data: u8) -> Result<(), Error<PinE, PinE>> {
+        for (i, d) in self.data_pins.iter_mut().enumerate() {
+            if ((data >> i) & 0b1) == 0b1 {
+                d.set_high().map_err(Error::OutputPin)?;
+            } else {
+                d.set_low().map_err(Error::OutputPin)?;
+            }
+        }
+        Ok(())
+    }
 }
 
 impl<'a, CSX, WRX, RDX, DCX, PinE> Interface
-	for Gpio8Interface<'_, &mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
+    for Gpio8Interface<'_, &mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
 where
-	CSX: OutputPin<Error = PinE>,
-	WRX: OutputPin<Error = PinE>,
-	RDX: OutputPin<Error = PinE>,
-	DCX: OutputPin<Error = PinE>,
+    CSX: OutputPin<Error = PinE>,
+    WRX: OutputPin<Error = PinE>,
+    RDX: OutputPin<Error = PinE>,
+    DCX: OutputPin<Error = PinE>,
 {
-	type Error = Error<PinE, PinE>;
+    type Error = Error<PinE, PinE>;
 
-	fn write(&mut self, command: u8, data: &[u8]) -> Result<(), Self::Error> {
-		self.csx.set_low().map_err(Error::OutputPin)?;
-		self.rdx.set_high().map_err(Error::OutputPin)?;
-		self.dcx.set_low().map_err(Error::OutputPin)?;
-		self.wrx.set_low().map_err(Error::OutputPin)?;
+    fn write(&mut self, command: u8, data: &[u8]) -> Result<(), Self::Error> {
+        self.csx.set_low().map_err(Error::OutputPin)?;
+        self.rdx.set_high().map_err(Error::OutputPin)?;
+        self.dcx.set_low().map_err(Error::OutputPin)?;
+        self.wrx.set_low().map_err(Error::OutputPin)?;
 
-		self.set_data_bus(command)?;
-		self.wrx.set_high().map_err(Error::OutputPin)?;
+        self.set_data_bus(command)?;
+        self.wrx.set_high().map_err(Error::OutputPin)?;
 
-		self.dcx.set_high().map_err(Error::OutputPin)?;
-		for val in data.iter() {
-			self.wrx.set_low().map_err(Error::OutputPin)?;
-			self.set_data_bus(*val)?;
-			self.wrx.set_high().map_err(Error::OutputPin)?;
-		}
+        self.dcx.set_high().map_err(Error::OutputPin)?;
+        for val in data.iter() {
+            self.wrx.set_low().map_err(Error::OutputPin)?;
+            self.set_data_bus(*val)?;
+            self.wrx.set_high().map_err(Error::OutputPin)?;
+        }
 
-		self.csx.set_high().map_err(Error::OutputPin)?;
+        self.csx.set_high().map_err(Error::OutputPin)?;
 
-		Ok(())
-	}
+        Ok(())
+    }
 
-	fn write_iter(
-		&mut self,
-		command: u8,
-		data: impl IntoIterator<Item = u16>,
-	) -> Result<(), Self::Error> {
-		self.csx.set_low().map_err(Error::OutputPin)?;
-		self.rdx.set_high().map_err(Error::OutputPin)?;
-		self.dcx.set_low().map_err(Error::OutputPin)?;
-		self.wrx.set_low().map_err(Error::OutputPin)?;
+    fn write_iter(
+        &mut self,
+        command: u8,
+        data: impl IntoIterator<Item = u16>,
+    ) -> Result<(), Self::Error> {
+        self.csx.set_low().map_err(Error::OutputPin)?;
+        self.rdx.set_high().map_err(Error::OutputPin)?;
+        self.dcx.set_low().map_err(Error::OutputPin)?;
+        self.wrx.set_low().map_err(Error::OutputPin)?;
 
-		self.set_data_bus(command)?;
-		self.wrx.set_high().map_err(Error::OutputPin)?;
+        self.set_data_bus(command)?;
+        self.wrx.set_high().map_err(Error::OutputPin)?;
 
-		self.dcx.set_high().map_err(Error::OutputPin)?;
-		for val in data.into_iter() {
-			for b in &val.to_be_bytes() {
-				self.wrx.set_low().map_err(Error::OutputPin)?;
-				self.set_data_bus(*b)?;
-				self.wrx.set_high().map_err(Error::OutputPin)?;
-			}
-		}
+        self.dcx.set_high().map_err(Error::OutputPin)?;
+        for val in data.into_iter() {
+            for b in &val.to_be_bytes() {
+                self.wrx.set_low().map_err(Error::OutputPin)?;
+                self.set_data_bus(*b)?;
+                self.wrx.set_high().map_err(Error::OutputPin)?;
+            }
+        }
 
-		self.csx.set_high().map_err(Error::OutputPin)?;
-		Ok(())
-	}
+        self.csx.set_high().map_err(Error::OutputPin)?;
+        Ok(())
+    }
 }
diff --git a/src/spi.rs b/src/spi.rs
index c168074..c249c11 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -1,7 +1,7 @@
+use crate::{Error, Interface};
 use embedded_hal::blocking::spi;
-use embedded_hal::spi::{Mode, Phase, Polarity};
 use embedded_hal::digital::v2::OutputPin;
-use crate::{Interface, Error};
+use embedded_hal::spi::{Mode, Phase, Polarity};
 
 /// SPI mode
 pub const MODE: Mode = Mode {
@@ -17,23 +17,21 @@ pub struct SpiInterface<SPI, CS, DC> {
 }
 
 impl<SPI, CS, DC, SpiE, PinE> SpiInterface<SPI, CS, DC>
-    where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
-          CS: OutputPin<Error = PinE>,
-          DC: OutputPin<Error = PinE>,
+where
+    SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
+    CS: OutputPin<Error = PinE>,
+    DC: OutputPin<Error = PinE>,
 {
     pub fn new(spi: SPI, cs: CS, dc: DC) -> Self {
-        Self {
-            spi,
-            cs,
-            dc,
-        }
+        Self { spi, cs, dc }
     }
 }
 
 impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC>
-    where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
-          CS: OutputPin<Error = PinE>,
-          DC: OutputPin<Error = PinE>,
+where
+    SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
+    CS: OutputPin<Error = PinE>,
+    DC: OutputPin<Error = PinE>,
 {
     type Error = Error<SpiE, PinE>;
 
@@ -50,7 +48,11 @@ impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC>
         Ok(())
     }
 
-    fn write_iter(&mut self, command: u8, data: impl IntoIterator<Item=u16>) -> Result<(), Self::Error> {
+    fn write_iter(
+        &mut self,
+        command: u8,
+        data: impl IntoIterator<Item = u16>,
+    ) -> Result<(), Self::Error> {
         self.cs.set_low().map_err(Error::OutputPin)?;
 
         self.dc.set_low().map_err(Error::OutputPin)?;