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Yuri Iozzelli 2020-03-01 16:45:00 +01:00
parent 651aba971b
commit 799dc143b8
2 changed files with 112 additions and 110 deletions
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192
src/gpio.rs
View file

@ -3,120 +3,120 @@ use embedded_hal::digital::v2::OutputPin;
/// `Interface` implementation for GPIO interfaces /// `Interface` implementation for GPIO interfaces
pub struct Gpio8Interface<'a, DATA, CSX, WRX, RDX, DCX> { pub struct Gpio8Interface<'a, DATA, CSX, WRX, RDX, DCX> {
data_pins: &'a mut [DATA; 8], data_pins: &'a mut [DATA; 8],
csx: CSX, csx: CSX,
wrx: WRX, wrx: WRX,
rdx: RDX, rdx: RDX,
dcx: DCX, dcx: DCX,
} }
impl<'a, CSX, WRX, RDX, DCX, PinE> impl<'a, CSX, WRX, RDX, DCX, PinE>
Gpio8Interface<'_, &'a mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX> Gpio8Interface<'_, &'a mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
where where
CSX: OutputPin<Error = PinE>, CSX: OutputPin<Error = PinE>,
WRX: OutputPin<Error = PinE>, WRX: OutputPin<Error = PinE>,
RDX: OutputPin<Error = PinE>, RDX: OutputPin<Error = PinE>,
DCX: OutputPin<Error = PinE>, DCX: OutputPin<Error = PinE>,
{ {
/// Create a new Gpio8Interface /// Create a new Gpio8Interface
/// ///
/// Example useage: /// Example useage:
/// ///
/// let csx = gpioc.pc2.into_push_pull_output(); /// let csx = gpioc.pc2.into_push_pull_output();
/// let wrx = gpiod.pd13.into_push_pull_output(); /// let wrx = gpiod.pd13.into_push_pull_output();
/// let rdx = gpiod.pd12.into_push_pull_output(); /// let rdx = gpiod.pd12.into_push_pull_output();
/// let dcx = gpiof.pf7.into_push_pull_output(); /// let dcx = gpiof.pf7.into_push_pull_output();
/// ///
/// let mut data_pins: [&mut dyn OutputPin<Error = _>; 8] = [ /// let mut data_pins: [&mut dyn OutputPin<Error = _>; 8] = [
/// &mut gpiod.pd6.into_push_pull_output(), /// &mut gpiod.pd6.into_push_pull_output(),
/// &mut gpiog.pg11.into_push_pull_output(), /// &mut gpiog.pg11.into_push_pull_output(),
/// ... /// ...
/// ]; /// ];
/// ///
/// let if_gpio = ili9341::gpio::Gpio8Interface::new(&mut data_pins, csx, wrx, rdx, dcx); /// let if_gpio = ili9341::gpio::Gpio8Interface::new(&mut data_pins, csx, wrx, rdx, dcx);
pub fn new( pub fn new(
data_pins: &'a mut [&'a mut dyn OutputPin<Error = PinE>; 8], data_pins: &'a mut [&'a mut dyn OutputPin<Error = PinE>; 8],
csx: CSX, csx: CSX,
wrx: WRX, wrx: WRX,
rdx: RDX, rdx: RDX,
dcx: DCX, dcx: DCX,
) -> Self { ) -> Self {
Self { Self {
data_pins, data_pins,
csx, csx,
wrx, wrx,
rdx, rdx,
dcx, dcx,
} }
} }
/// Sets the gpio data pins used in the parallel interface /// Sets the gpio data pins used in the parallel interface
fn set_data_bus(&mut self, data: u8) -> Result<(), Error<PinE, PinE>> { fn set_data_bus(&mut self, data: u8) -> Result<(), Error<PinE, PinE>> {
for (i, d) in self.data_pins.iter_mut().enumerate() { for (i, d) in self.data_pins.iter_mut().enumerate() {
if ((data >> i) & 0b1) == 0b1 { if ((data >> i) & 0b1) == 0b1 {
d.set_high().map_err(Error::OutputPin)?; d.set_high().map_err(Error::OutputPin)?;
} else { } else {
d.set_low().map_err(Error::OutputPin)?; d.set_low().map_err(Error::OutputPin)?;
} }
} }
Ok(()) Ok(())
} }
} }
impl<'a, CSX, WRX, RDX, DCX, PinE> Interface impl<'a, CSX, WRX, RDX, DCX, PinE> Interface
for Gpio8Interface<'_, &mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX> for Gpio8Interface<'_, &mut dyn OutputPin<Error = PinE>, CSX, WRX, RDX, DCX>
where where
CSX: OutputPin<Error = PinE>, CSX: OutputPin<Error = PinE>,
WRX: OutputPin<Error = PinE>, WRX: OutputPin<Error = PinE>,
RDX: OutputPin<Error = PinE>, RDX: OutputPin<Error = PinE>,
DCX: OutputPin<Error = PinE>, DCX: OutputPin<Error = PinE>,
{ {
type Error = Error<PinE, PinE>; type Error = Error<PinE, PinE>;
fn write(&mut self, command: u8, data: &[u8]) -> Result<(), Self::Error> { fn write(&mut self, command: u8, data: &[u8]) -> Result<(), Self::Error> {
self.csx.set_low().map_err(Error::OutputPin)?; self.csx.set_low().map_err(Error::OutputPin)?;
self.rdx.set_high().map_err(Error::OutputPin)?; self.rdx.set_high().map_err(Error::OutputPin)?;
self.dcx.set_low().map_err(Error::OutputPin)?; self.dcx.set_low().map_err(Error::OutputPin)?;
self.wrx.set_low().map_err(Error::OutputPin)?; self.wrx.set_low().map_err(Error::OutputPin)?;
self.set_data_bus(command)?; self.set_data_bus(command)?;
self.wrx.set_high().map_err(Error::OutputPin)?; self.wrx.set_high().map_err(Error::OutputPin)?;
self.dcx.set_high().map_err(Error::OutputPin)?; self.dcx.set_high().map_err(Error::OutputPin)?;
for val in data.iter() { for val in data.iter() {
self.wrx.set_low().map_err(Error::OutputPin)?; self.wrx.set_low().map_err(Error::OutputPin)?;
self.set_data_bus(*val)?; self.set_data_bus(*val)?;
self.wrx.set_high().map_err(Error::OutputPin)?; self.wrx.set_high().map_err(Error::OutputPin)?;
} }
self.csx.set_high().map_err(Error::OutputPin)?; self.csx.set_high().map_err(Error::OutputPin)?;
Ok(()) Ok(())
} }
fn write_iter( fn write_iter(
&mut self, &mut self,
command: u8, command: u8,
data: impl IntoIterator<Item = u16>, data: impl IntoIterator<Item = u16>,
) -> Result<(), Self::Error> { ) -> Result<(), Self::Error> {
self.csx.set_low().map_err(Error::OutputPin)?; self.csx.set_low().map_err(Error::OutputPin)?;
self.rdx.set_high().map_err(Error::OutputPin)?; self.rdx.set_high().map_err(Error::OutputPin)?;
self.dcx.set_low().map_err(Error::OutputPin)?; self.dcx.set_low().map_err(Error::OutputPin)?;
self.wrx.set_low().map_err(Error::OutputPin)?; self.wrx.set_low().map_err(Error::OutputPin)?;
self.set_data_bus(command)?; self.set_data_bus(command)?;
self.wrx.set_high().map_err(Error::OutputPin)?; self.wrx.set_high().map_err(Error::OutputPin)?;
self.dcx.set_high().map_err(Error::OutputPin)?; self.dcx.set_high().map_err(Error::OutputPin)?;
for val in data.into_iter() { for val in data.into_iter() {
for b in &val.to_be_bytes() { for b in &val.to_be_bytes() {
self.wrx.set_low().map_err(Error::OutputPin)?; self.wrx.set_low().map_err(Error::OutputPin)?;
self.set_data_bus(*b)?; self.set_data_bus(*b)?;
self.wrx.set_high().map_err(Error::OutputPin)?; self.wrx.set_high().map_err(Error::OutputPin)?;
} }
} }
self.csx.set_high().map_err(Error::OutputPin)?; self.csx.set_high().map_err(Error::OutputPin)?;
Ok(()) Ok(())
} }
} }

30
src/spi.rs
View file

@ -1,7 +1,7 @@
use crate::{Error, Interface};
use embedded_hal::blocking::spi; use embedded_hal::blocking::spi;
use embedded_hal::spi::{Mode, Phase, Polarity};
use embedded_hal::digital::v2::OutputPin; use embedded_hal::digital::v2::OutputPin;
use crate::{Interface, Error}; use embedded_hal::spi::{Mode, Phase, Polarity};
/// SPI mode /// SPI mode
pub const MODE: Mode = Mode { pub const MODE: Mode = Mode {
@ -17,23 +17,21 @@ pub struct SpiInterface<SPI, CS, DC> {
} }
impl<SPI, CS, DC, SpiE, PinE> SpiInterface<SPI, CS, DC> impl<SPI, CS, DC, SpiE, PinE> SpiInterface<SPI, CS, DC>
where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>, where
CS: OutputPin<Error = PinE>, SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
DC: OutputPin<Error = PinE>, CS: OutputPin<Error = PinE>,
DC: OutputPin<Error = PinE>,
{ {
pub fn new(spi: SPI, cs: CS, dc: DC) -> Self { pub fn new(spi: SPI, cs: CS, dc: DC) -> Self {
Self { Self { spi, cs, dc }
spi,
cs,
dc,
}
} }
} }
impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC> impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC>
where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>, where
CS: OutputPin<Error = PinE>, SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
DC: OutputPin<Error = PinE>, CS: OutputPin<Error = PinE>,
DC: OutputPin<Error = PinE>,
{ {
type Error = Error<SpiE, PinE>; type Error = Error<SpiE, PinE>;
@ -50,7 +48,11 @@ impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC>
Ok(()) Ok(())
} }
fn write_iter(&mut self, command: u8, data: impl IntoIterator<Item=u16>) -> Result<(), Self::Error> { fn write_iter(
&mut self,
command: u8,
data: impl IntoIterator<Item = u16>,
) -> Result<(), Self::Error> {
self.cs.set_low().map_err(Error::OutputPin)?; self.cs.set_low().map_err(Error::OutputPin)?;
self.dc.set_low().map_err(Error::OutputPin)?; self.dc.set_low().map_err(Error::OutputPin)?;