mirror of
https://github.com/yuri91/ili9341-rs.git
synced 2024-11-25 08:00:59 +00:00
Move SPI interface implementation into a separate file
This commit is contained in:
parent
f09403d092
commit
5b03a86bb0
2 changed files with 79 additions and 54 deletions
66
src/lib.rs
66
src/lib.rs
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@ -6,13 +6,15 @@ extern crate embedded_hal as hal;
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extern crate embedded_graphics;
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extern crate embedded_graphics;
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use hal::blocking::delay::DelayMs;
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use hal::blocking::delay::DelayMs;
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use hal::blocking::spi;
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use hal::blocking::spi::{Write, Transfer};
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use hal::digital::v2::OutputPin;
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use hal::digital::v2::OutputPin;
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use hal::spi::{Mode, Phase, Polarity};
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use core::fmt::Debug;
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use core::fmt::Debug;
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use core::iter::IntoIterator;
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use core::iter::IntoIterator;
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pub mod spi;
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use spi::SpiInterface;
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/// Trait representing the interface to the hardware.
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/// Trait representing the interface to the hardware.
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///
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///
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/// Intended to abstract the various buses (SPI, MPU 8/9/16-bit) from the Controller code.
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/// Intended to abstract the various buses (SPI, MPU 8/9/16-bit) from the Controller code.
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@ -31,12 +33,6 @@ pub trait Interface {
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fn write_iter(&mut self, command: u8, data: impl IntoIterator<Item = u16>) -> Result<(), Self::Error>;
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fn write_iter(&mut self, command: u8, data: impl IntoIterator<Item = u16>) -> Result<(), Self::Error>;
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}
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}
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/// SPI mode
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pub const MODE: Mode = Mode {
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polarity: Polarity::IdleLow,
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phase: Phase::CaptureOnFirstTransition,
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};
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const WIDTH: usize = 240;
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const WIDTH: usize = 240;
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const HEIGHT: usize = 320;
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const HEIGHT: usize = 320;
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@ -71,9 +67,7 @@ pub enum Orientation {
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/// and the next word will fill the next pixel (the adjacent on the right, or
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/// and the next word will fill the next pixel (the adjacent on the right, or
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/// the first of the next row if the row ended)
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/// the first of the next row if the row ended)
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pub struct Ili9341<SPI, CS, DC, RESET> {
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pub struct Ili9341<SPI, CS, DC, RESET> {
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spi: SPI,
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interface: SpiInterface<SPI, CS, DC>,
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cs: CS,
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dc: DC,
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reset: RESET,
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reset: RESET,
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width: usize,
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width: usize,
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height: usize,
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height: usize,
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@ -81,7 +75,7 @@ pub struct Ili9341<SPI, CS, DC, RESET> {
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impl<SpiE, PinE, SPI, CS, DC, RESET> Ili9341<SPI, CS, DC, RESET>
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impl<SpiE, PinE, SPI, CS, DC, RESET> Ili9341<SPI, CS, DC, RESET>
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where
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where
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SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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SPI: Transfer<u8, Error = SpiE> + Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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RESET: OutputPin<Error = PinE>,
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RESET: OutputPin<Error = PinE>,
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@ -93,10 +87,9 @@ where
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reset: RESET,
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reset: RESET,
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delay: &mut DELAY,
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delay: &mut DELAY,
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) -> Result<Self, Error<SpiE, PinE>> {
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) -> Result<Self, Error<SpiE, PinE>> {
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let interface = SpiInterface::new(spi, cs, dc);
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let mut ili9341 = Ili9341 {
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let mut ili9341 = Ili9341 {
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spi,
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interface,
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cs,
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dc,
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reset,
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reset,
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width: WIDTH,
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width: WIDTH,
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height: HEIGHT,
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height: HEIGHT,
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@ -159,51 +152,16 @@ where
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Ok(())
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Ok(())
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}
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}
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fn command(&mut self, cmd: Command, args: &[u8]) -> Result<(), Error<SpiE, PinE>> {
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fn command(&mut self, cmd: Command, args: &[u8]) -> Result<(), Error<SpiE, PinE>> {
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self.cs.set_low().map_err(Error::OutputPin)?;
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self.interface.write(cmd as u8, args)
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self.dc.set_low().map_err(Error::OutputPin)?;
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self.spi.write(&[cmd as u8]).map_err(Error::Spi)?;
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self.dc.set_high().map_err(Error::OutputPin)?;
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self.spi.write(args).map_err(Error::Spi)?;
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self.cs.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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}
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fn write_iter<I: IntoIterator<Item = u16>>(
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fn write_iter<I: IntoIterator<Item = u16>>(
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&mut self,
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&mut self,
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data: I,
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data: I,
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) -> Result<(), Error<SpiE, PinE>> {
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) -> Result<(), Error<SpiE, PinE>> {
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self.cs.set_low().map_err(Error::OutputPin)?;
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self.interface.write_iter(Command::MemoryWrite as u8, data)
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self.dc.set_low().map_err(Error::OutputPin)?;
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self.spi
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.write(&[Command::MemoryWrite as u8])
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.map_err(Error::Spi)?;
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self.dc.set_high().map_err(Error::OutputPin)?;
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for d in data.into_iter() {
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self.spi
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.write(&[(d >> 8) as u8, (d & 0xff) as u8])
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.map_err(Error::Spi)?;
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}
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self.cs.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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}
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fn write_raw(&mut self, data: &[u8]) -> Result<(), Error<SpiE, PinE>> {
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fn write_raw(&mut self, data: &[u8]) -> Result<(), Error<SpiE, PinE>> {
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self.cs.set_low().map_err(Error::OutputPin)?;
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self.interface.write(Command::MemoryWrite as u8, data)
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self.dc.set_low().map_err(Error::OutputPin)?;
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self.spi
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.write(&[Command::MemoryWrite as u8])
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.map_err(Error::Spi)?;
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self.dc.set_high().map_err(Error::OutputPin)?;
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self.spi.write(data).map_err(Error::Spi)?;
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self.cs.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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}
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fn set_window(&mut self, x0: u16, y0: u16, x1: u16, y1: u16) -> Result<(), Error<SpiE, PinE>> {
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fn set_window(&mut self, x0: u16, y0: u16, x1: u16, y1: u16) -> Result<(), Error<SpiE, PinE>> {
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self.command(
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self.command(
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@ -310,7 +268,7 @@ use embedded_graphics::{drawable::Pixel, pixelcolor::Rgb565, Drawing};
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#[cfg(feature = "graphics")]
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#[cfg(feature = "graphics")]
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impl<SpiE, PinE, SPI, CS, DC, RESET> Drawing<Rgb565> for Ili9341<SPI, CS, DC, RESET>
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impl<SpiE, PinE, SPI, CS, DC, RESET> Drawing<Rgb565> for Ili9341<SPI, CS, DC, RESET>
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where
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where
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SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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SPI: Transfer<u8, Error = SpiE> + Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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RESET: OutputPin<Error = PinE>,
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RESET: OutputPin<Error = PinE>,
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67
src/spi.rs
Normal file
67
src/spi.rs
Normal file
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@ -0,0 +1,67 @@
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use super::hal::blocking::spi;
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use super::hal::spi::{Mode, Phase, Polarity};
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use super::hal::digital::v2::OutputPin;
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use super::{Interface, Error};
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/// SPI mode
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pub const MODE: Mode = Mode {
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polarity: Polarity::IdleLow,
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phase: Phase::CaptureOnFirstTransition,
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};
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/// `Interface` implementation for SPI interfaces
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pub struct SpiInterface<SPI, CS, DC> {
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spi: SPI,
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cs: CS,
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dc: DC,
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}
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impl<SPI, CS, DC, SpiE, PinE> SpiInterface<SPI, CS, DC>
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where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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{
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pub fn new(spi: SPI, cs: CS, dc: DC) -> Self {
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Self {
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spi,
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cs,
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dc,
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}
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}
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}
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impl<SPI, CS, DC, SpiE, PinE> Interface for SpiInterface<SPI, CS, DC>
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where SPI: spi::Transfer<u8, Error = SpiE> + spi::Write<u8, Error = SpiE>,
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CS: OutputPin<Error = PinE>,
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DC: OutputPin<Error = PinE>,
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{
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type Error = Error<SpiE, PinE>;
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fn write(&mut self, command: u8, data: &[u8]) -> Result<(), Self::Error> {
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self.cs.set_low().map_err(Error::OutputPin)?;
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self.dc.set_low().map_err(Error::OutputPin)?;
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self.spi.write(&[command]).map_err(Error::Spi)?;
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self.dc.set_high().map_err(Error::OutputPin)?;
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self.spi.write(data).map_err(Error::Spi)?;
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self.cs.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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fn write_iter(&mut self, command: u8, data: impl IntoIterator<Item=u16>) -> Result<(), Self::Error> {
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self.cs.set_low().map_err(Error::OutputPin)?;
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self.dc.set_low().map_err(Error::OutputPin)?;
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self.spi.write(&[command]).map_err(Error::Spi)?;
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self.dc.set_high().map_err(Error::OutputPin)?;
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for w in data.into_iter() {
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self.spi.write(&w.to_be_bytes()).map_err(Error::Spi)?;
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}
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self.cs.set_high().map_err(Error::OutputPin)?;
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Ok(())
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}
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}
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