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Original commit message from CVS: * gst/deinterlace2/tvtime/greedyh.asm: * gst/deinterlace2/tvtime/greedyh.c: (greedyDScaler_C), (deinterlace_frame_di_greedyh), (dscaler_greedyh_get_method): * gst/deinterlace2/tvtime/greedyhmacros.h: Add a C implementation for the greedyh deinterlacing method, clean up the code a bit and mark the SSE version as MMXEXT as it doesn't require any SSE instructions.
74 lines
3.7 KiB
C
74 lines
3.7 KiB
C
/////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2001 Tom Barry. All rights reserved.
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/////////////////////////////////////////////////////////////////////////////
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//
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// This file is subject to the terms of the GNU General Public License as
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// published by the Free Software Foundation. A copy of this license is
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// included with this software distribution in the file COPYING. If you
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// do not have a copy, you may obtain a copy by writing to the Free
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// Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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//
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// This software is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details
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//
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/////////////////////////////////////////////////////////////////////////////
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// Define a few macros for CPU dependent instructions.
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// I suspect I don't really understand how the C macro preprocessor works but
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// this seems to get the job done. // TRB 7/01
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// BEFORE USING THESE YOU MUST SET:
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// #define SIMD_TYPE MMXEXT (or MMX or TDNOW)
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// some macros for pavgb instruction
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// V_PAVGB(mmr1, mmr2, mmr work register, smask) mmr2 may = mmrw if you can trash it
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#define V_PAVGB_MMX(mmr1, mmr2, mmrw, smask) \
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"movq "mmr2", "mmrw"\n\t" \
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"pand "smask", "mmrw"\n\t" \
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"psrlw $1, "mmrw"\n\t" \
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"pand "smask", "mmr1"\n\t" \
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"psrlw $1, "mmr1"\n\t" \
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"paddusb "mmrw", "mmr1"\n\t"
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#define V_PAVGB_MMXEXT(mmr1, mmr2, mmrw, smask) "pavgb "mmr2", "mmr1"\n\t"
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#define V_PAVGB_TDNOW(mmr1, mmr2, mmrw, smask) "pavgusb "mmr2", "mmr1"\n\t"
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#define V_PAVGB(mmr1, mmr2, mmrw, smask) V_PAVGB2(mmr1, mmr2, mmrw, smask, SIMD_TYPE)
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#define V_PAVGB2(mmr1, mmr2, mmrw, smask, simdtype) V_PAVGB3(mmr1, mmr2, mmrw, smask, simdtype)
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#define V_PAVGB3(mmr1, mmr2, mmrw, smask, simdtype) V_PAVGB_##simdtype(mmr1, mmr2, mmrw, smask)
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// some macros for pmaxub instruction
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#define V_PMAXUB_MMX(mmr1, mmr2) \
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"psubusb "mmr2", "mmr1"\n\t" \
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"paddusb "mmr2", "mmr1"\n\t"
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#define V_PMAXUB_MMXEXT(mmr1, mmr2) "pmaxub "mmr2", "mmr1"\n\t"
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#define V_PMAXUB_TDNOW(mmr1, mmr2) V_PMAXUB_MMX(mmr1, mmr2) // use MMX version
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#define V_PMAXUB(mmr1, mmr2) V_PMAXUB2(mmr1, mmr2, SIMD_TYPE)
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#define V_PMAXUB2(mmr1, mmr2, simdtype) V_PMAXUB3(mmr1, mmr2, simdtype)
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#define V_PMAXUB3(mmr1, mmr2, simdtype) V_PMAXUB_##simdtype(mmr1, mmr2)
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// some macros for pminub instruction
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// V_PMINUB(mmr1, mmr2, mmr work register) mmr2 may NOT = mmrw
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#define V_PMINUB_MMX(mmr1, mmr2, mmrw) \
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"pcmpeqb "mmrw", "mmrw"\n\t" \
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"psubusb "mmr2", "mmrw"\n\t" \
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"paddusb "mmrw", "mmr1"\n\t" \
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"psubusb "mmrw", "mmr1"\n\t"
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#define V_PMINUB_MMXEXT(mmr1, mmr2, mmrw) "pminub "mmr2", "mmr1"\n\t"
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#define V_PMINUB_TDNOW(mmr1, mmr2, mmrw) V_PMINUB_MMX(mmr1, mmr2, mmrw) // use MMX version
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#define V_PMINUB(mmr1, mmr2, mmrw) V_PMINUB2(mmr1, mmr2, mmrw, SIMD_TYPE)
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#define V_PMINUB2(mmr1, mmr2, mmrw, simdtype) V_PMINUB3(mmr1, mmr2, mmrw, simdtype)
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#define V_PMINUB3(mmr1, mmr2, mmrw, simdtype) V_PMINUB_##simdtype(mmr1, mmr2, mmrw)
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// some macros for movntq instruction
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// V_MOVNTQ(mmr1, mmr2)
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#define V_MOVNTQ_MMX(mmr1, mmr2) "movq "mmr2", "mmr1"\n\t"
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#define V_MOVNTQ_TDNOW(mmr1, mmr2) "movq "mmr2", "mmr1"\n\t"
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#define V_MOVNTQ_MMXEXT(mmr1, mmr2) "movntq "mmr2", "mmr1"\n\t"
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#define V_MOVNTQ(mmr1, mmr2) V_MOVNTQ2(mmr1, mmr2, SIMD_TYPE)
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#define V_MOVNTQ2(mmr1, mmr2, simdtype) V_MOVNTQ3(mmr1, mmr2, simdtype)
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#define V_MOVNTQ3(mmr1, mmr2, simdtype) V_MOVNTQ_##simdtype(mmr1, mmr2)
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// end of macros
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