268 lines
9.7 KiB
C
268 lines
9.7 KiB
C
#include <stdio.h>
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#include <string.h>
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#include <sdkconfig.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/queue.h>
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#include <esp_system.h>
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#include <esp_err.h>
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#include <esp_log.h>
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#include "driver/uart.h"
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#include "hardware.h"
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#include "managed_i2c.h"
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#include "pax_gfx.h"
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#include "ice40.h"
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#include "system_wrapper.h"
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#include "graphics_wrapper.h"
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#include "esp32/rom/crc.h"
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void fpga_install_uart() {
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fflush(stdout);
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ESP_ERROR_CHECK(uart_driver_install(0, 2048, 0, 0, NULL, 0));
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uart_config_t uart_config = {
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.baud_rate = 921600,
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.data_bits = UART_DATA_8_BITS,
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.parity = UART_PARITY_DISABLE,
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.stop_bits = UART_STOP_BITS_1,
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.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
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.source_clk = UART_SCLK_APB,
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};
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ESP_ERROR_CHECK(uart_param_config(0, &uart_config));
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}
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void fpga_uninstall_uart() {
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uart_driver_delete(0);
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}
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bool fpga_read_stdin(uint8_t* buffer, uint32_t len, uint32_t timeout) {
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int read = uart_read_bytes(0, buffer, len, timeout / portTICK_PERIOD_MS);
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return (read == len);
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}
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bool fpga_uart_sync(uint32_t* length, uint32_t* crc) {
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uint8_t data[256];
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uart_read_bytes(0, data, sizeof(data), 10 / portTICK_PERIOD_MS);
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char command[] = "FPGA";
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uart_write_bytes(0, command, 4);
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uint8_t rx_buffer[4 * 3];
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fpga_read_stdin(rx_buffer, sizeof(rx_buffer), 1000);
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if (memcmp(rx_buffer, "FPGA", 4) != 0) return false;
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memcpy((uint8_t*) length, &rx_buffer[4 * 1], 4);
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memcpy((uint8_t*) crc, &rx_buffer[4 * 2], 4);
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return true;
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}
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bool fpga_uart_load(uint8_t* buffer, uint32_t length) {
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return fpga_read_stdin(buffer, length, 3000);
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}
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void fpga_uart_mess(const char *mess) {
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uart_write_bytes(0, mess, strlen(mess));
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}
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esp_err_t fpga_process_events(xQueueHandle buttonQueue, ICE40* ice40, uint16_t *key_state, uint16_t *idle_count)
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{
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rp2040_input_message_t buttonMessage = {0};
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while (xQueueReceive(buttonQueue, &buttonMessage, 0) == pdTRUE) {
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uint8_t pin = buttonMessage.input;
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bool value = buttonMessage.state;
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uint16_t key_mask = 0;
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switch(pin) {
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case RP2040_INPUT_JOYSTICK_DOWN:
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key_mask = 1 << 0;
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break;
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case RP2040_INPUT_JOYSTICK_UP:
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key_mask = 1 << 1;
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break;
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case RP2040_INPUT_JOYSTICK_LEFT:
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key_mask = 1 << 2;
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break;
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case RP2040_INPUT_JOYSTICK_RIGHT:
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key_mask = 1 << 3;
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break;
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case RP2040_INPUT_JOYSTICK_PRESS:
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key_mask = 1 << 4;
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break;
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case RP2040_INPUT_BUTTON_HOME:
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key_mask = 1 << 5;
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break;
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case RP2040_INPUT_BUTTON_MENU:
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key_mask = 1 << 6;
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break;
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case RP2040_INPUT_BUTTON_SELECT:
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key_mask = 1 << 7;
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break;
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case RP2040_INPUT_BUTTON_START:
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key_mask = 1 << 8;
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break;
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case RP2040_INPUT_BUTTON_ACCEPT:
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key_mask = 1 << 9;
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break;
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case RP2040_INPUT_BUTTON_BACK:
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key_mask = 1 << 10;
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default:
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break;
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}
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if (key_mask != 0)
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{
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if (value) {
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*key_state |= key_mask;
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}
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else {
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*key_state &= ~key_mask;
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}
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uint8_t spi_message[5] = { 0xf4 };
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spi_message[1] = *key_state >> 8;
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spi_message[2] = *key_state & 0xff;
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spi_message[3] = key_mask >> 8;
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spi_message[4] = key_mask & 0xff;
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esp_err_t res = ice40_send(ice40, spi_message, 5);
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if (res != ESP_OK) {
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return res;
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}
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}
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*idle_count = 0;
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}
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return ESP_OK;
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}
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void fpga_download(xQueueHandle buttonQueue, ICE40* ice40, pax_buf_t* pax_buffer, ILI9341* ili9341) {
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char message[64];
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0x325aa8);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, "Preparing...");
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ili9341_write(ili9341, pax_buffer->buf);
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fpga_install_uart();
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ice40_disable(ice40);
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ili9341_init(ili9341);
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uint8_t counter = 0;
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uint32_t length = 0;
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uint32_t crc = 0;
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while (!fpga_uart_sync(&length, &crc)) {
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0x325aa8);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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snprintf(message, sizeof(message), "Waiting for bitstream%s%s%s", (counter > 0) ? "." : " ", (counter > 1) ? "." : " ", (counter > 2) ? "." : " ");
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, message);
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ili9341_write(ili9341, pax_buffer->buf);
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counter++;
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if (counter > 3) counter = 0;
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}
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while (true) {
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0x325aa8);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, "Receiving bitstream...");
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ili9341_write(ili9341, pax_buffer->buf);
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uint8_t* buffer = malloc(length);
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if (buffer == NULL) {
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0xa85a32);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, "Malloc failed");
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ili9341_write(ili9341, pax_buffer->buf);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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fpga_uninstall_uart();
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return;
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}
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if (!fpga_uart_load(buffer, length)) {
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free(buffer);
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0xa85a32);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, "Timeout while loading");
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ili9341_write(ili9341, pax_buffer->buf);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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fpga_uninstall_uart();
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return;
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}
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uint32_t checkCrc = crc32_le(0, buffer, length);
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if (checkCrc != crc) {
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free(buffer);
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0xa85a32);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, "CRC incorrect");
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snprintf(message, sizeof(message), "Provided CRC: %08X", crc);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*2, message);
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snprintf(message, sizeof(message), "Calculated CRC: %08X", checkCrc);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*3, message);
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ili9341_write(ili9341, pax_buffer->buf);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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snprintf(message, sizeof(message), "CRC incorrect %08X %08x\n", crc, checkCrc);
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fpga_uart_mess(message);
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fpga_uninstall_uart();
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return;
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}
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fpga_uart_mess("CRC correct\n");
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ili9341_deinit(ili9341);
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ili9341_select(ili9341, false);
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vTaskDelay(200 / portTICK_PERIOD_MS);
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ili9341_select(ili9341, true);
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esp_err_t res = ice40_load_bitstream(ice40, buffer, length);
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free(buffer);
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if (res != ESP_OK) {
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ice40_disable(ice40);
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ili9341_init(ili9341);
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0xa85a32);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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snprintf(message, sizeof(message), "Upload failed: %d", res);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, message);
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ili9341_write(ili9341, pax_buffer->buf);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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snprintf(message, sizeof(message), "uploading bitstream failed with %d\n", res);
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fpga_uart_mess(message);
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fpga_uninstall_uart();
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return;
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}
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snprintf(message, sizeof(message), "bitstream has uploaded\n");
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fpga_uart_mess(message);
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// Waiting for next download and sending key strokes to FPGA
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uint16_t key_state = 0;
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uint16_t idle_count = 0;
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while (true) {
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if (idle_count >= 200) {
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if (fpga_uart_sync(&length, &crc)) {
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break;
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}
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idle_count = 0;
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}
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esp_err_t res = fpga_process_events(buttonQueue, ice40, &key_state, &idle_count);
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if (res != ESP_OK) {
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ice40_disable(ice40);
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ili9341_init(ili9341);
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pax_noclip(pax_buffer);
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pax_background(pax_buffer, 0xa85a32);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*0, "FPGA download mode");
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snprintf(message, sizeof(message), "Error: %d", res);
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pax_draw_text(pax_buffer, 0xFFFFFFFF, NULL, 18, 0, 20*1, message);
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ili9341_write(ili9341, pax_buffer->buf);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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snprintf(message, sizeof(message), "processing events failed with %d\n", res);
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fpga_uart_mess(message);
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fpga_uninstall_uart();
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return;
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}
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vTaskDelay(10 / portTICK_PERIOD_MS);
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idle_count++;
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}
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ice40_disable(ice40);
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ili9341_init(ili9341);
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}
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}
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