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https://gitlab.freedesktop.org/gstreamer/gstreamer.git
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cef201734c
Adding a new element for texture conversion from single mip level texture to mipmapping enabled RGBA texture Part-of: <https://gitlab.freedesktop.org/gstreamer/gstreamer/-/merge_requests/7555>
421 lines
17 KiB
HLSL
421 lines
17 KiB
HLSL
/**
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* MIT License
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*
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* Copyright (c) 2018 Jeremiah van Oosten
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/* Source: https://github.com/jpvanoosten/LearningDirectX12 */
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#ifdef BUILDING_HLSL
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#define BLOCK_SIZE 8
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// When reducing the size of a texture, it could be that downscaling the texture
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// will result in a less than exactly 50% (1/2) of the original texture size.
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// This happens if either the width, or the height (or both) dimensions of the texture
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// are odd. For example, downscaling a 5x3 texture will result in a 2x1 texture which
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// has a 60% reduction in the texture width and 66% reduction in the height.
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// When this happens, we need to take more samples from the source texture to
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// determine the pixel value in the destination texture.
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#define WIDTH_HEIGHT_EVEN 0 // Both the width and the height of the texture are even.
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#define WIDTH_ODD_HEIGHT_EVEN 1 // The texture width is odd and the height is even.
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#define WIDTH_EVEN_HEIGHT_ODD 2 // The texture width is even and teh height is odd.
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#define WIDTH_HEIGHT_ODD 3 // Both the width and height of the texture are odd.
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struct ComputeShaderInput
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{
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uint3 GroupID : SV_GroupID; // 3D index of the thread group in the dispatch.
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uint3 GroupThreadID : SV_GroupThreadID; // 3D index of local thread ID in a thread group.
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uint3 DispatchThreadID : SV_DispatchThreadID; // 3D index of global thread ID in the dispatch.
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uint GroupIndex : SV_GroupIndex; // Flattened local index of the thread within a thread group.
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};
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cbuffer GenerateMipsCB : register( b0 )
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{
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uint SrcMipLevel; // Texture level of source mip
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uint NumMipLevels; // Number of OutMips to write: [1-4]
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uint SrcDimension; // Width and height of the source texture are even or odd.
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uint padding;
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float2 TexelSize; // 1.0 / OutMip1.Dimensions
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}
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// Source mip map.
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Texture2D<float4> SrcMip : register( t0 );
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// Write up to 4 mip map levels.
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RWTexture2D<float4> OutMip1 : register( u0 );
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RWTexture2D<float4> OutMip2 : register( u1 );
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RWTexture2D<float4> OutMip3 : register( u2 );
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RWTexture2D<float4> OutMip4 : register( u3 );
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// Linear clamp sampler.
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SamplerState LinearClampSampler : register( s0 );
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// The reason for separating channels is to reduce bank conflicts in the
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// local data memory controller. A large stride will cause more threads
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// to collide on the same memory bank.
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groupshared float gs_R[64];
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groupshared float gs_G[64];
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groupshared float gs_B[64];
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groupshared float gs_A[64];
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void StoreColor( uint Index, float4 Color )
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{
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gs_R[Index] = Color.r;
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gs_G[Index] = Color.g;
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gs_B[Index] = Color.b;
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gs_A[Index] = Color.a;
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}
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float4 LoadColor( uint Index )
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{
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return float4( gs_R[Index], gs_G[Index], gs_B[Index], gs_A[Index] );
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}
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[numthreads( BLOCK_SIZE, BLOCK_SIZE, 1 )]
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void ENTRY_POINT( ComputeShaderInput IN )
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{
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float4 Src1 = (float4)0;
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// One bilinear sample is insufficient when scaling down by more than 2x.
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// You will slightly undersample in the case where the source dimension
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// is odd. This is why it's a really good idea to only generate mips on
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// power-of-two sized textures. Trying to handle the undersampling case
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// will force this shader to be slower and more complicated as it will
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// have to take more source texture samples.
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// Determine the path to use based on the dimension of the
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// source texture.
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// 0b00(0): Both width and height are even.
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// 0b01(1): Width is odd, height is even.
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// 0b10(2): Width is even, height is odd.
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// 0b11(3): Both width and height are odd.
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switch ( SrcDimension )
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{
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case WIDTH_HEIGHT_EVEN:
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{
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float2 UV = TexelSize * ( IN.DispatchThreadID.xy + 0.5 );
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Src1 = SrcMip.SampleLevel( LinearClampSampler, UV, SrcMipLevel );
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}
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break;
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case WIDTH_ODD_HEIGHT_EVEN:
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{
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// > 2:1 in X dimension
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// Use 2 bilinear samples to guarantee we don't undersample when downsizing by more than 2x
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// horizontally.
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float2 UV1 = TexelSize * ( IN.DispatchThreadID.xy + float2( 0.25, 0.5 ) );
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float2 Off = TexelSize * float2( 0.5, 0.0 );
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Src1 = 0.5 * ( SrcMip.SampleLevel( LinearClampSampler, UV1, SrcMipLevel ) +
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SrcMip.SampleLevel( LinearClampSampler, UV1 + Off, SrcMipLevel ) );
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}
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break;
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case WIDTH_EVEN_HEIGHT_ODD:
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{
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// > 2:1 in Y dimension
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// Use 2 bilinear samples to guarantee we don't undersample when downsizing by more than 2x
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// vertically.
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float2 UV1 = TexelSize * ( IN.DispatchThreadID.xy + float2( 0.5, 0.25 ) );
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float2 Off = TexelSize * float2( 0.0, 0.5 );
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Src1 = 0.5 * ( SrcMip.SampleLevel( LinearClampSampler, UV1, SrcMipLevel ) +
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SrcMip.SampleLevel( LinearClampSampler, UV1 + Off, SrcMipLevel ) );
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}
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break;
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case WIDTH_HEIGHT_ODD:
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{
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// > 2:1 in in both dimensions
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// Use 4 bilinear samples to guarantee we don't undersample when downsizing by more than 2x
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// in both directions.
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float2 UV1 = TexelSize * ( IN.DispatchThreadID.xy + float2( 0.25, 0.25 ) );
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float2 Off = TexelSize * 0.5;
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Src1 = SrcMip.SampleLevel( LinearClampSampler, UV1, SrcMipLevel );
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Src1 += SrcMip.SampleLevel( LinearClampSampler, UV1 + float2( Off.x, 0.0 ), SrcMipLevel );
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Src1 += SrcMip.SampleLevel( LinearClampSampler, UV1 + float2( 0.0, Off.y ), SrcMipLevel );
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Src1 += SrcMip.SampleLevel( LinearClampSampler, UV1 + float2( Off.x, Off.y ), SrcMipLevel );
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Src1 *= 0.25;
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}
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break;
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}
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OutMip1[IN.DispatchThreadID.xy] = Src1;
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// A scalar (constant) branch can exit all threads coherently.
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if ( NumMipLevels == 1 )
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return;
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// Without lane swizzle operations, the only way to share data with other
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// threads is through LDS.
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StoreColor( IN.GroupIndex, Src1 );
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// This guarantees all LDS writes are complete and that all threads have
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// executed all instructions so far (and therefore have issued their LDS
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// write instructions.)
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GroupMemoryBarrierWithGroupSync();
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// With low three bits for X and high three bits for Y, this bit mask
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// (binary: 001001) checks that X and Y are even.
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if ( ( IN.GroupIndex & 0x9 ) == 0 )
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{
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float4 Src2 = LoadColor( IN.GroupIndex + 0x01 );
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float4 Src3 = LoadColor( IN.GroupIndex + 0x08 );
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float4 Src4 = LoadColor( IN.GroupIndex + 0x09 );
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Src1 = 0.25 * ( Src1 + Src2 + Src3 + Src4 );
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OutMip2[IN.DispatchThreadID.xy / 2] = Src1;
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StoreColor( IN.GroupIndex, Src1 );
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}
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if ( NumMipLevels == 2 )
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return;
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GroupMemoryBarrierWithGroupSync();
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// This bit mask (binary: 011011) checks that X and Y are multiples of four.
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if ( ( IN.GroupIndex & 0x1B ) == 0 )
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{
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float4 Src2 = LoadColor( IN.GroupIndex + 0x02 );
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float4 Src3 = LoadColor( IN.GroupIndex + 0x10 );
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float4 Src4 = LoadColor( IN.GroupIndex + 0x12 );
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Src1 = 0.25 * ( Src1 + Src2 + Src3 + Src4 );
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OutMip3[IN.DispatchThreadID.xy / 4] = Src1;
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StoreColor( IN.GroupIndex, Src1 );
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}
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if ( NumMipLevels == 3 )
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return;
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GroupMemoryBarrierWithGroupSync();
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// This bit mask would be 111111 (X & Y multiples of 8), but only one
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// thread fits that criteria.
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if ( IN.GroupIndex == 0 )
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{
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float4 Src2 = LoadColor( IN.GroupIndex + 0x04 );
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float4 Src3 = LoadColor( IN.GroupIndex + 0x20 );
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float4 Src4 = LoadColor( IN.GroupIndex + 0x24 );
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Src1 = 0.25 * ( Src1 + Src2 + Src3 + Src4 );
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OutMip4[IN.DispatchThreadID.xy / 8] = Src1;
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}
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}
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#else
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static const char str_CSMain_mipgen[] =
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"#define BLOCK_SIZE 8\n"
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"\n"
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" // When reducing the size of a texture, it could be that downscaling the texture\n"
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" // will result in a less than exactly 50% (1/2) of the original texture size.\n"
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" // This happens if either the width, or the height (or both) dimensions of the texture\n"
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" // are odd. For example, downscaling a 5x3 texture will result in a 2x1 texture which\n"
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" // has a 60% reduction in the texture width and 66% reduction in the height.\n"
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" // When this happens, we need to take more samples from the source texture to\n"
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" // determine the pixel value in the destination texture.\n"
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"\n"
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"#define WIDTH_HEIGHT_EVEN 0 // Both the width and the height of the texture are even.\n"
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"#define WIDTH_ODD_HEIGHT_EVEN 1 // The texture width is odd and the height is even.\n"
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"#define WIDTH_EVEN_HEIGHT_ODD 2 // The texture width is even and teh height is odd.\n"
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"#define WIDTH_HEIGHT_ODD 3 // Both the width and height of the texture are odd.\n"
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"\n"
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"struct ComputeShaderInput\n"
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"{\n"
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" uint3 GroupID : SV_GroupID; // 3D index of the thread group in the dispatch.\n"
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" uint3 GroupThreadID : SV_GroupThreadID; // 3D index of local thread ID in a thread group.\n"
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" uint3 DispatchThreadID : SV_DispatchThreadID; // 3D index of global thread ID in the dispatch.\n"
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" uint GroupIndex : SV_GroupIndex; // Flattened local index of the thread within a thread group.\n"
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"};\n"
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"\n"
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"cbuffer GenerateMipsCB : register( b0 )\n"
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"{\n"
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" uint SrcMipLevel; // Texture level of source mip\n"
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" uint NumMipLevels; // Number of OutMips to write: [1-4]\n"
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" uint SrcDimension; // Width and height of the source texture are even or odd.\n"
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" uint padding;\n"
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" float2 TexelSize; // 1.0 / OutMip1.Dimensions\n"
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"}\n"
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"\n"
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"// Source mip map.\n"
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"Texture2D<float4> SrcMip : register( t0 );\n"
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"\n"
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"// Write up to 4 mip map levels.\n"
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"RWTexture2D<float4> OutMip1 : register( u0 );\n"
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"RWTexture2D<float4> OutMip2 : register( u1 );\n"
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"RWTexture2D<float4> OutMip3 : register( u2 );\n"
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"RWTexture2D<float4> OutMip4 : register( u3 );\n"
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"\n"
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"// Linear clamp sampler.\n"
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"SamplerState LinearClampSampler : register( s0 );\n"
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"\n"
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"// The reason for separating channels is to reduce bank conflicts in the\n"
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"// local data memory controller. A large stride will cause more threads\n"
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"// to collide on the same memory bank.\n"
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"groupshared float gs_R[64];\n"
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"groupshared float gs_G[64];\n"
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"groupshared float gs_B[64];\n"
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"groupshared float gs_A[64];\n"
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"\n"
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"void StoreColor( uint Index, float4 Color )\n"
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"{\n"
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" gs_R[Index] = Color.r;\n"
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" gs_G[Index] = Color.g;\n"
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" gs_B[Index] = Color.b;\n"
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" gs_A[Index] = Color.a;\n"
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"}\n"
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"\n"
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"float4 LoadColor( uint Index )\n"
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"{\n"
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" return float4( gs_R[Index], gs_G[Index], gs_B[Index], gs_A[Index] );\n"
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"}\n"
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"\n"
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"[numthreads( BLOCK_SIZE, BLOCK_SIZE, 1 )]\n"
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"void ENTRY_POINT( ComputeShaderInput IN )\n"
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"{\n"
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" float4 Src1 = (float4)0;\n"
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"\n"
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" // One bilinear sample is insufficient when scaling down by more than 2x.\n"
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" // You will slightly undersample in the case where the source dimension\n"
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" // is odd. This is why it's a really good idea to only generate mips on\n"
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" // power-of-two sized textures. Trying to handle the undersampling case\n"
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" // will force this shader to be slower and more complicated as it will\n"
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" // have to take more source texture samples.\n"
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"\n"
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" // Determine the path to use based on the dimension of the\n"
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" // source texture.\n"
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" // 0b00(0): Both width and height are even.\n"
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" // 0b01(1): Width is odd, height is even.\n"
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" // 0b10(2): Width is even, height is odd.\n"
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" // 0b11(3): Both width and height are odd.\n"
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" switch ( SrcDimension )\n"
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" {\n"
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" case WIDTH_HEIGHT_EVEN:\n"
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" {\n"
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" float2 UV = TexelSize * ( IN.DispatchThreadID.xy + 0.5 );\n"
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"\n"
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" Src1 = SrcMip.SampleLevel( LinearClampSampler, UV, SrcMipLevel );\n"
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" }\n"
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" break;\n"
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" case WIDTH_ODD_HEIGHT_EVEN:\n"
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" {\n"
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" // > 2:1 in X dimension\n"
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" // Use 2 bilinear samples to guarantee we don't undersample when downsizing by more than 2x\n"
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" // horizontally.\n"
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" float2 UV1 = TexelSize * ( IN.DispatchThreadID.xy + float2( 0.25, 0.5 ) );\n"
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" float2 Off = TexelSize * float2( 0.5, 0.0 );\n"
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"\n"
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" Src1 = 0.5 * ( SrcMip.SampleLevel( LinearClampSampler, UV1, SrcMipLevel ) +\n"
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" SrcMip.SampleLevel( LinearClampSampler, UV1 + Off, SrcMipLevel ) );\n"
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" }\n"
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" break;\n"
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" case WIDTH_EVEN_HEIGHT_ODD:\n"
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" {\n"
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" // > 2:1 in Y dimension\n"
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" // Use 2 bilinear samples to guarantee we don't undersample when downsizing by more than 2x\n"
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" // vertically.\n"
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" float2 UV1 = TexelSize * ( IN.DispatchThreadID.xy + float2( 0.5, 0.25 ) );\n"
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" float2 Off = TexelSize * float2( 0.0, 0.5 );\n"
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"\n"
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" Src1 = 0.5 * ( SrcMip.SampleLevel( LinearClampSampler, UV1, SrcMipLevel ) +\n"
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" SrcMip.SampleLevel( LinearClampSampler, UV1 + Off, SrcMipLevel ) );\n"
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" }\n"
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" break;\n"
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" case WIDTH_HEIGHT_ODD:\n"
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" {\n"
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" // > 2:1 in in both dimensions\n"
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" // Use 4 bilinear samples to guarantee we don't undersample when downsizing by more than 2x\n"
|
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" // in both directions.\n"
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" float2 UV1 = TexelSize * ( IN.DispatchThreadID.xy + float2( 0.25, 0.25 ) );\n"
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" float2 Off = TexelSize * 0.5;\n"
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"\n"
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" Src1 = SrcMip.SampleLevel( LinearClampSampler, UV1, SrcMipLevel );\n"
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" Src1 += SrcMip.SampleLevel( LinearClampSampler, UV1 + float2( Off.x, 0.0 ), SrcMipLevel );\n"
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" Src1 += SrcMip.SampleLevel( LinearClampSampler, UV1 + float2( 0.0, Off.y ), SrcMipLevel );\n"
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" Src1 += SrcMip.SampleLevel( LinearClampSampler, UV1 + float2( Off.x, Off.y ), SrcMipLevel );\n"
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" Src1 *= 0.25;\n"
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" }\n"
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" break;\n"
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" }\n"
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"\n"
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" OutMip1[IN.DispatchThreadID.xy] = Src1;\n"
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"\n"
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" // A scalar (constant) branch can exit all threads coherently.\n"
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" if ( NumMipLevels == 1 )\n"
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" return;\n"
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"\n"
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" // Without lane swizzle operations, the only way to share data with other\n"
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" // threads is through LDS.\n"
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" StoreColor( IN.GroupIndex, Src1 );\n"
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"\n"
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" // This guarantees all LDS writes are complete and that all threads have\n"
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" // executed all instructions so far (and therefore have issued their LDS\n"
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" // write instructions.)\n"
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" GroupMemoryBarrierWithGroupSync();\n"
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"\n"
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" // With low three bits for X and high three bits for Y, this bit mask\n"
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" // (binary: 001001) checks that X and Y are even.\n"
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" if ( ( IN.GroupIndex & 0x9 ) == 0 )\n"
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" {\n"
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" float4 Src2 = LoadColor( IN.GroupIndex + 0x01 );\n"
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" float4 Src3 = LoadColor( IN.GroupIndex + 0x08 );\n"
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" float4 Src4 = LoadColor( IN.GroupIndex + 0x09 );\n"
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" Src1 = 0.25 * ( Src1 + Src2 + Src3 + Src4 );\n"
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"\n"
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" OutMip2[IN.DispatchThreadID.xy / 2] = Src1;\n"
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" StoreColor( IN.GroupIndex, Src1 );\n"
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" }\n"
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"\n"
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" if ( NumMipLevels == 2 )\n"
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" return;\n"
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"\n"
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" GroupMemoryBarrierWithGroupSync();\n"
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"\n"
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" // This bit mask (binary: 011011) checks that X and Y are multiples of four.\n"
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" if ( ( IN.GroupIndex & 0x1B ) == 0 )\n"
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" {\n"
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" float4 Src2 = LoadColor( IN.GroupIndex + 0x02 );\n"
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" float4 Src3 = LoadColor( IN.GroupIndex + 0x10 );\n"
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" float4 Src4 = LoadColor( IN.GroupIndex + 0x12 );\n"
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" Src1 = 0.25 * ( Src1 + Src2 + Src3 + Src4 );\n"
|
|
"\n"
|
|
" OutMip3[IN.DispatchThreadID.xy / 4] = Src1;\n"
|
|
" StoreColor( IN.GroupIndex, Src1 );\n"
|
|
" }\n"
|
|
"\n"
|
|
" if ( NumMipLevels == 3 )\n"
|
|
" return;\n"
|
|
"\n"
|
|
" GroupMemoryBarrierWithGroupSync();\n"
|
|
"\n"
|
|
" // This bit mask would be 111111 (X & Y multiples of 8), but only one\n"
|
|
" // thread fits that criteria.\n"
|
|
" if ( IN.GroupIndex == 0 )\n"
|
|
" {\n"
|
|
" float4 Src2 = LoadColor( IN.GroupIndex + 0x04 );\n"
|
|
" float4 Src3 = LoadColor( IN.GroupIndex + 0x20 );\n"
|
|
" float4 Src4 = LoadColor( IN.GroupIndex + 0x24 );\n"
|
|
" Src1 = 0.25 * ( Src1 + Src2 + Src3 + Src4 );\n"
|
|
"\n"
|
|
" OutMip4[IN.DispatchThreadID.xy / 8] = Src1;\n"
|
|
" }\n"
|
|
"}\n";
|
|
#endif
|