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Original commit message from CVS: 2008-02-23 Bastien Nocera <hadess@hadess.net> * configure.ac: Add checks for Flex/Yacc/Bison and other furry animals, for the new goom 2k4 based plugin * gst/goom/*: Update to use goom 2k4, uses liboil to detect CPU optimisations (not working yet), move the old plugin to... * gst/goom2k1/*: ... here, in case somebody is sick enough Fixes #515073
537 lines
15 KiB
C
537 lines
15 KiB
C
/* xmmx.h
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eXtended MultiMedia eXtensions GCC interface library for IA32.
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To use this library, simply include this header file
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and compile with GCC. You MUST have inlining enabled
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in order for xmmx_ok() to work; this can be done by
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simply using -O on the GCC command line.
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Compiling with -DXMMX_TRACE will cause detailed trace
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output to be sent to stderr for each mmx operation.
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This adds lots of code, and obviously slows execution to
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a crawl, but can be very useful for debugging.
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THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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AND FITNESS FOR ANY PARTICULAR PURPOSE.
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1999 by R. Fisher
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Based on libmmx, 1997-99 by H. Dietz and R. Fisher
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Notes:
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It appears that the latest gas has the pand problem fixed, therefore
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I'll undefine BROKEN_PAND by default.
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*/
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#ifndef _XMMX_H
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#define _XMMX_H
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/* Warning: at this writing, the version of GAS packaged
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with most Linux distributions does not handle the
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parallel AND operation mnemonic correctly. If the
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symbol BROKEN_PAND is defined, a slower alternative
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coding will be used. If execution of mmxtest results
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in an illegal instruction fault, define this symbol.
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*/
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#undef BROKEN_PAND
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/* The type of an value that fits in an (Extended) MMX register
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(note that long long constant values MUST be suffixed
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by LL and unsigned long long values by ULL, lest
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they be truncated by the compiler)
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*/
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#ifndef _MMX_H
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typedef union {
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long long q; /* Quadword (64-bit) value */
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unsigned long long uq; /* Unsigned Quadword */
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int d[2]; /* 2 Doubleword (32-bit) values */
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unsigned int ud[2]; /* 2 Unsigned Doubleword */
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short w[4]; /* 4 Word (16-bit) values */
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unsigned short uw[4]; /* 4 Unsigned Word */
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char b[8]; /* 8 Byte (8-bit) values */
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unsigned char ub[8]; /* 8 Unsigned Byte */
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float s[2]; /* Single-precision (32-bit) value */
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} __attribute__ ((aligned (8))) mmx_t; /* On an 8-byte (64-bit) boundary */
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#endif
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/* Function to test if multimedia instructions are supported...
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*/
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static int
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mm_support(void)
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{
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/* Returns 1 if MMX instructions are supported,
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3 if Cyrix MMX and Extended MMX instructions are supported
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5 if AMD MMX and 3DNow! instructions are supported
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0 if hardware does not support any of these
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*/
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register int rval = 0;
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__asm__ __volatile__ (
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/* See if CPUID instruction is supported ... */
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/* ... Get copies of EFLAGS into eax and ecx */
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"pushf\n\t"
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"popl %%eax\n\t"
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"movl %%eax, %%ecx\n\t"
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/* ... Toggle the ID bit in one copy and store */
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/* to the EFLAGS reg */
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"xorl $0x200000, %%eax\n\t"
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"push %%eax\n\t"
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"popf\n\t"
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/* ... Get the (hopefully modified) EFLAGS */
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"pushf\n\t"
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"popl %%eax\n\t"
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/* ... Compare and test result */
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"xorl %%eax, %%ecx\n\t"
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"testl $0x200000, %%ecx\n\t"
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"jz NotSupported1\n\t" /* CPUID not supported */
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/* Get standard CPUID information, and
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go to a specific vendor section */
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"movl $0, %%eax\n\t"
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"cpuid\n\t"
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/* Check for Intel */
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"cmpl $0x756e6547, %%ebx\n\t"
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"jne TryAMD\n\t"
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"cmpl $0x49656e69, %%edx\n\t"
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"jne TryAMD\n\t"
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"cmpl $0x6c65746e, %%ecx\n"
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"jne TryAMD\n\t"
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"jmp Intel\n\t"
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/* Check for AMD */
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"\nTryAMD:\n\t"
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"cmpl $0x68747541, %%ebx\n\t"
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"jne TryCyrix\n\t"
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"cmpl $0x69746e65, %%edx\n\t"
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"jne TryCyrix\n\t"
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"cmpl $0x444d4163, %%ecx\n"
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"jne TryCyrix\n\t"
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"jmp AMD\n\t"
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/* Check for Cyrix */
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"\nTryCyrix:\n\t"
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"cmpl $0x69727943, %%ebx\n\t"
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"jne NotSupported2\n\t"
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"cmpl $0x736e4978, %%edx\n\t"
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"jne NotSupported3\n\t"
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"cmpl $0x64616574, %%ecx\n\t"
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"jne NotSupported4\n\t"
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/* Drop through to Cyrix... */
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/* Cyrix Section */
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/* See if extended CPUID level 80000001 is supported */
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/* The value of CPUID/80000001 for the 6x86MX is undefined
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according to the Cyrix CPU Detection Guide (Preliminary
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Rev. 1.01 table 1), so we'll check the value of eax for
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CPUID/0 to see if standard CPUID level 2 is supported.
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According to the table, the only CPU which supports level
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2 is also the only one which supports extended CPUID levels.
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*/
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"cmpl $0x2, %%eax\n\t"
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"jne MMXtest\n\t" /* Use standard CPUID instead */
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/* Extended CPUID supported (in theory), so get extended
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features */
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"movl $0x80000001, %%eax\n\t"
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"cpuid\n\t"
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"testl $0x00800000, %%eax\n\t" /* Test for MMX */
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"jz NotSupported5\n\t" /* MMX not supported */
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"testl $0x01000000, %%eax\n\t" /* Test for Ext'd MMX */
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"jnz EMMXSupported\n\t"
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"movl $1, %0:\n\n\t" /* MMX Supported */
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"jmp Return\n\n"
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"EMMXSupported:\n\t"
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"movl $3, %0:\n\n\t" /* EMMX and MMX Supported */
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"jmp Return\n\t"
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/* AMD Section */
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"AMD:\n\t"
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/* See if extended CPUID is supported */
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"movl $0x80000000, %%eax\n\t"
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"cpuid\n\t"
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"cmpl $0x80000000, %%eax\n\t"
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"jl MMXtest\n\t" /* Use standard CPUID instead */
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/* Extended CPUID supported, so get extended features */
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"movl $0x80000001, %%eax\n\t"
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"cpuid\n\t"
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"testl $0x00800000, %%edx\n\t" /* Test for MMX */
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"jz NotSupported6\n\t" /* MMX not supported */
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"testl $0x80000000, %%edx\n\t" /* Test for 3DNow! */
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"jnz ThreeDNowSupported\n\t"
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"movl $1, %0:\n\n\t" /* MMX Supported */
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"jmp Return\n\n"
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"ThreeDNowSupported:\n\t"
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"movl $5, %0:\n\n\t" /* 3DNow! and MMX Supported */
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"jmp Return\n\t"
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/* Intel Section */
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"Intel:\n\t"
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/* Check for MMX */
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"MMXtest:\n\t"
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"movl $1, %%eax\n\t"
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"cpuid\n\t"
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"testl $0x00800000, %%edx\n\t" /* Test for MMX */
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"jz NotSupported7\n\t" /* MMX Not supported */
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"movl $1, %0:\n\n\t" /* MMX Supported */
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"jmp Return\n\t"
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/* Nothing supported */
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"\nNotSupported1:\n\t"
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"#movl $101, %0:\n\n\t"
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"\nNotSupported2:\n\t"
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"#movl $102, %0:\n\n\t"
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"\nNotSupported3:\n\t"
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"#movl $103, %0:\n\n\t"
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"\nNotSupported4:\n\t"
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"#movl $104, %0:\n\n\t"
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"\nNotSupported5:\n\t"
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"#movl $105, %0:\n\n\t"
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"\nNotSupported6:\n\t"
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"#movl $106, %0:\n\n\t"
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"\nNotSupported7:\n\t"
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"#movl $107, %0:\n\n\t"
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"movl $0, %0:\n\n\t"
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"Return:\n\t"
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: "=a" (rval)
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: /* no input */
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: "eax", "ebx", "ecx", "edx"
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);
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/* Return */
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return(rval);
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}
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/* Function to test if mmx instructions are supported...
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*/
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#ifndef _XMMX_H
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inline extern int
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mmx_ok(void)
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{
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/* Returns 1 if MMX instructions are supported, 0 otherwise */
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return ( mm_support() & 0x1 );
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}
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#endif
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/* Function to test if xmmx instructions are supported...
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*/
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inline extern int
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xmmx_ok(void)
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{
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/* Returns 1 if Extended MMX instructions are supported, 0 otherwise */
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return ( (mm_support() & 0x2) >> 1 );
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}
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/* Helper functions for the instruction macros that follow...
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(note that memory-to-register, m2r, instructions are nearly
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as efficient as register-to-register, r2r, instructions;
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however, memory-to-memory instructions are really simulated
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as a convenience, and are only 1/3 as efficient)
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*/
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#ifdef XMMX_TRACE
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/* Include the stuff for printing a trace to stderr...
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*/
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#include <stdio.h>
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#define mmx_i2r(op, imm, reg) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace.uq = (imm); \
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fprintf(stderr, #op "_i2r(" #imm "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (imm)); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_m2r(op, mem, reg) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mem); \
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fprintf(stderr, #op "_m2r(" #mem "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (mem)); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_r2m(op, reg, mem) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2m(" #reg "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=X" (mem) \
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: /* nothing */ ); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_r2r(op, regs, regd) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #regs ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2r(" #regs "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#define mmx_m2m(op, mems, memd) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mems); \
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fprintf(stderr, #op "_m2m(" #mems "=0x%08x%08x, ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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mmx_trace = (memd); \
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fprintf(stderr, #memd "=0x%08x%08x) => ", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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#op " %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (memd) \
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: "X" (mems)); \
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mmx_trace = (memd); \
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fprintf(stderr, #memd "=0x%08x%08x\n", \
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mmx_trace.d[1], mmx_trace.d[0]); \
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}
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#else
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/* These macros are a lot simpler without the tracing...
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*/
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#define mmx_i2r(op, imm, reg) \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (imm) )
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#define mmx_m2r(op, mem, reg) \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (mem))
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#define mmx_m2ir(op, mem, rs) \
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__asm__ __volatile__ (#op " %0, %%" #rs \
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: /* nothing */ \
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: "X" (mem) )
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#define mmx_r2m(op, reg, mem) \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=X" (mem) \
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: /* nothing */ )
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#define mmx_r2r(op, regs, regd) \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd)
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#define mmx_r2ir(op, rs1, rs2) \
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__asm__ __volatile__ (#op " %%" #rs1 ", %%" #rs2 \
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: /* nothing */ \
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: /* nothing */ )
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#define mmx_m2m(op, mems, memd) \
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__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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#op " %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (memd) \
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: "X" (mems))
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#endif
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/* 1x64 MOVe Quadword
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(this is both a load and a store...
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in fact, it is the only way to store)
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*/
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#define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
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#define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
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#define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
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#define movq(vars, vard) \
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__asm__ __volatile__ ("movq %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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/* 1x32 MOVe Doubleword
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(like movq, this is both load and store...
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but is most useful for moving things between
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mmx registers and ordinary registers)
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*/
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#define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
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#define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
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#define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
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#define movd(vars, vard) \
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__asm__ __volatile__ ("movd %1, %%mm0\n\t" \
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"movd %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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/* 4x16 Parallel MAGnitude
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*/
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#define pmagw_m2r(var, reg) mmx_m2r(pmagw, var, reg)
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#define pmagw_r2r(regs, regd) mmx_r2r(pmagw, regs, regd)
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#define pmagw(vars, vard) mmx_m2m(pmagw, vars, vard)
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/* 4x16 Parallel ADDs using Saturation arithmetic
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and Implied destination
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*/
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#define paddsiw_m2ir(var, rs) mmx_m2ir(paddsiw, var, rs)
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#define paddsiw_r2ir(rs1, rs2) mmx_r2ir(paddsiw, rs1, rs2)
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#define paddsiw(vars, vard) mmx_m2m(paddsiw, vars, vard)
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/* 4x16 Parallel SUBs using Saturation arithmetic
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and Implied destination
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*/
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#define psubsiw_m2ir(var, rs) mmx_m2ir(psubsiw, var, rs)
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#define psubsiw_r2ir(rs1, rs2) mmx_r2ir(psubsiw, rs1, rs2)
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#define psubsiw(vars, vard) mmx_m2m(psubsiw, vars, vard)
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/* 4x16 Parallel MULs giving High 4x16 portions of results
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Rounded with 1/2 bit 15.
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*/
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#define pmulhrw_m2r(var, reg) mmx_m2r(pmulhrw, var, reg)
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#define pmulhrw_r2r(regs, regd) mmx_r2r(pmulhrw, regs, regd)
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#define pmulhrw(vars, vard) mmx_m2m(pmulhrw, vars, vard)
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/* 4x16 Parallel MULs giving High 4x16 portions of results
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Rounded with 1/2 bit 15, storing to Implied register
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*/
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#define pmulhriw_m2ir(var, rs) mmx_m2ir(pmulhriw, var, rs)
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#define pmulhriw_r2ir(rs1, rs2) mmx_r2ir(pmulhriw, rs1, rs2)
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#define pmulhriw(vars, vard) mmx_m2m(pmulhriw, vars, vard)
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/* 4x16 Parallel Muls (and ACcumulate) giving High 4x16 portions
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of results Rounded with 1/2 bit 15, accumulating with Implied register
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*/
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#define pmachriw_m2ir(var, rs) mmx_m2ir(pmachriw, var, rs)
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#define pmachriw_r2ir(rs1, rs2) mmx_r2ir(pmachriw, rs1, rs2)
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#define pmachriw(vars, vard) mmx_m2m(pmachriw, vars, vard)
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/* 8x8u Parallel AVErage
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*/
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#define paveb_m2r(var, reg) mmx_m2r(paveb, var, reg)
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#define paveb_r2r(regs, regd) mmx_r2r(paveb, regs, regd)
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#define paveb(vars, vard) mmx_m2m(paveb, vars, vard)
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/* 8x8u Parallel DISTance and accumulate with
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unsigned saturation to Implied register
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*/
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#define pdistib_m2ir(var, rs) mmx_m2ir(pdistib, var, rs)
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#define pdistib(vars, vard) mmx_m2m(pdistib, vars, vard)
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/* 8x8 Parallel conditional MoVe
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if implied register field is Zero
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*/
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#define pmvzb_m2ir(var, rs) mmx_m2ir(pmvzb, var, rs)
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/* 8x8 Parallel conditional MoVe
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if implied register field is Not Zero
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*/
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#define pmvnzb_m2ir(var, rs) mmx_m2ir(pmvnzb, var, rs)
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/* 8x8 Parallel conditional MoVe
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if implied register field is Less than Zero
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*/
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#define pmvlzb_m2ir(var, rs) mmx_m2ir(pmvlzb, var, rs)
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/* 8x8 Parallel conditional MoVe
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if implied register field is Greater than or Equal to Zero
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*/
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#define pmvgezb_m2ir(var, rs) mmx_m2ir(pmvgezb, var, rs)
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/* Fast Empty MMx State
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(used to clean-up when going from mmx to float use
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of the registers that are shared by both; note that
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there is no float-to-xmmx operation needed, because
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only the float tag word info is corruptible)
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*/
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#ifdef XMMX_TRACE
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#define femms() \
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{ \
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fprintf(stderr, "femms()\n"); \
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__asm__ __volatile__ ("femms"); \
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}
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#else
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#define femms() __asm__ __volatile__ ("femms")
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#endif
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#endif
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