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https://gitlab.freedesktop.org/gstreamer/gstreamer.git
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523 lines
14 KiB
C
523 lines
14 KiB
C
/* GStreamer
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* Copyright (C) 1999, 2003 Erik Walthinsen <omega@cse.ogi.edu>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Library General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Library General Public License for more details.
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*
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* You should have received a copy of the GNU Library General Public
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* License along with this library; if not, write to the
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* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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* Boston, MA 02111-1307, USA.
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*
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*
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* Much of the code in this file is taken from the Linux kernel.
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* The code is relicensed under the LGPL with the kind permission of
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* Linus Torvalds,Ralf Baechle and Alan Cox
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*/
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#ifndef __GST_ATOMIC_IMPL_H__
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#define __GST_ATOMIC_IMPL_H__
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <glib.h>
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#include "gstatomic.h"
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#include "gstmacros.h"
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G_BEGIN_DECLS
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#if defined (GST_CAN_INLINE) || defined (__GST_ATOMIC_C__)
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/***** Intel x86 *****/
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#if (defined (HAVE_CPU_I386) || defined (HAVE_CPU_X86_64)) && defined(__GNUC__)
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#ifdef GST_CONFIG_NO_SMP
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#define SMP_LOCK ""
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#else
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#define SMP_LOCK "lock ; "
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#endif
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GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
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GST_INLINE_FUNC void gst_atomic_int_set (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC gint gst_atomic_int_read (GstAtomicInt *aint) { return aint->counter; }
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GST_INLINE_FUNC void
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gst_atomic_int_add (GstAtomicInt *aint, gint val)
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{
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__asm__ __volatile__(
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SMP_LOCK "addl %1,%0"
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:"=m" (aint->counter)
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:"ir" (val), "m" (aint->counter));
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}
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GST_INLINE_FUNC void
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gst_atomic_int_inc (GstAtomicInt *aint)
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{
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__asm__ __volatile__(
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SMP_LOCK "incl %0"
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:"=m" (aint->counter)
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:"m" (aint->counter));
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}
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GST_INLINE_FUNC gboolean
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gst_atomic_int_dec_and_test (GstAtomicInt *aint)
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{
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guchar res;
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__asm__ __volatile__(
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SMP_LOCK "decl %0; sete %1"
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:"=m" (aint->counter), "=qm" (res)
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:"m" (aint->counter) : "memory");
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return res != 0;
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}
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/***** PowerPC *****/
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#elif defined (HAVE_CPU_PPC) && defined(__GNUC__)
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#ifdef GST_CONFIG_NO_SMP
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#define SMP_SYNC ""
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#define SMP_ISYNC
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#else
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#define SMP_SYNC "\tsync\n"
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#define SMP_ISYNC "\tisync\n"
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#endif
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/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
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* The old ATOMIC_SYNC_FIX covered some but not all of this.
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*/
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#ifdef GST_CONFIG_IBM405_ERR77
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#define PPC405_ERR77(ra,rb) "\tdcbt " #ra "," #rb "\n"
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#else
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#define PPC405_ERR77(ra,rb)
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#endif
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GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
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GST_INLINE_FUNC void gst_atomic_int_set (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC gint gst_atomic_int_read (GstAtomicInt *aint) { return aint->counter; }
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GST_INLINE_FUNC void
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gst_atomic_int_add (GstAtomicInt *aint, gint val)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3\n"
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" add %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n"
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" bne- 1b\n"
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: "=&r" (t), "=m" (aint->counter)
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: "r" (val), "r" (&aint->counter), "m" (aint->counter)
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: "cc");
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}
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GST_INLINE_FUNC void
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gst_atomic_int_inc (GstAtomicInt *aint)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2\n"
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" addic %0,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2\n"
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" bne- 1b\n"
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: "=&r" (t), "=m" (aint->counter)
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: "r" (&aint->counter), "m" (aint->counter)
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: "cc");
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}
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GST_INLINE_FUNC gboolean
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gst_atomic_int_dec_and_test (GstAtomicInt *aint)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%1\n"
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" addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n"
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" bne- 1b\n"
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SMP_ISYNC
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: "=&r" (t)
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: "r" (&aint->counter)
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: "cc", "memory");
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return t == 0;
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}
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/***** DEC[/Compaq/HP?/Intel?] Alpha *****/
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#elif defined(HAVE_CPU_ALPHA) && defined(__GNUC__)
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GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
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GST_INLINE_FUNC void gst_atomic_int_set (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC gint gst_atomic_int_read (GstAtomicInt *aint) { return aint->counter; }
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GST_INLINE_FUNC void
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gst_atomic_int_add (GstAtomicInt *aint, gint val)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" addl %0,%2,%0\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (aint->counter)
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:"Ir" (val), "m" (aint->counter));
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}
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GST_INLINE_FUNC void
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gst_atomic_int_inc (GstAtomicInt *aint)
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{
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gst_atomic_int_add (aint, 1);
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}
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GST_INLINE_FUNC gboolean
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gst_atomic_int_dec_and_test (GstAtomicInt *aint)
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{
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long temp, result;
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int val = 1;
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" subl %0,%3,%2\n"
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" subl %0,%3,%0\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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" mb\n"
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (aint->counter), "=&r" (result)
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:"Ir" (val), "m" (aint->counter) : "memory");
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return result == 0;
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}
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/***** Sun SPARC *****/
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#elif 0 && defined(HAVE_CPU_SPARC) && defined(__GNUC__)
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/* allegedly broken again */
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GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
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#ifdef GST_CONFIG_NO_SMP
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GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC void gst_atomic_int_set (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC gint gst_atomic_int_read (GstAtomicInt *aint) { return aint->counter; }
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#else
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GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = (val<<8); }
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GST_INLINE_FUNC void gst_atomic_int_set (GstAtomicInt *aint, gint val) { aint->counter = (val<<8); }
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/*
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* For SMP the trick is you embed the spin lock byte within
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* the word, use the low byte so signedness is easily retained
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* via a quick arithmetic shift. It looks like this:
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*
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* ----------------------------------------
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* | signed 24-bit counter value | lock | atomic_t
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* ----------------------------------------
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* 31 8 7 0
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*/
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GST_INLINE_FUNC gint
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gst_atomic_int_read (GstAtomicInt *aint)
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{
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int ret = aint->counter;
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while (ret & 0xff)
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ret = aint->counter;
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return ret >> 8;
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}
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#endif /* GST_CONFIG_NO_SMP */
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GST_INLINE_FUNC void
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gst_atomic_int_add (GstAtomicInt *aint, gint val)
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{
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volatile int increment, *ptr;
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int lock = 1;
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int ignore = 0;
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ptr = &(aint->counter);
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#if __GNUC__ > 3 || (__GNUC__ >=3 && __GNUC_MINOR__ >= 2)
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__asm__ __volatile__("1: ldstub [%[ptr] + 3], %[lock]\n"
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"\torcc %[lock], 0, %[ignore]\n"
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"\tbne 1b\n" /* go back until we have the lock */
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"\tld [%[ptr]], %[inc]\n"
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"\tsra %[inc], 8, %[inc]\n"
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"\tadd %[inc], %[val], %[inc]\n"
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"\tsll %[inc], 8, %[lock]\n"
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"\tst %[lock],[%[ptr]]\n" /* Release the lock */
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: [inc] "=&r" (increment), [lock] "=r" (lock),
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[ignore] "=&r" (ignore)
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: "0" (increment), [ptr] "r" (ptr), [val] "r" (val)
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);
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#else
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__asm__ __volatile__("1: ldstub [%4 + 3], %1\n"
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"\torcc %1, 0, %2\n"
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"\tbne 1b\n" /* go back until we have the lock */
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"\tld [%4], %0\n"
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"\tsra %0, 8, %0\n"
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"\tadd %0, %5, %0\n"
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"\tsll %0, 8, %1\n"
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"\tst %1,[%4]\n" /* Release the lock */
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: "=&r" (increment), "=r" (lock), "=&r" (ignore)
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: "0" (increment), "r" (ptr), "r" (val)
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);
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#endif
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}
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GST_INLINE_FUNC void
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gst_atomic_int_inc (GstAtomicInt *aint)
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{
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gst_atomic_int_add (aint, 1);
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}
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GST_INLINE_FUNC gboolean
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gst_atomic_int_dec_and_test (GstAtomicInt *aint)
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{
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volatile int increment, *ptr;
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int lock = 1;
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int ignore = 0;
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ptr = &aint->counter;
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#if __GNUC__ > 3 || (__GNUC__ >=3 && __GNUC_MINOR__ >= 2)
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__asm__ __volatile__("1: ldstub [%[ptr] + 3], %[lock]\n"
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"\torcc %[lock], 0, %[ignore]\n"
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"\tbne 1b\n" /* go back until we have the lock */
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"\tld [%[ptr]], %[inc]\n"
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"\tsra %[inc], 8, %[inc]\n"
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"\tsub %[inc], 1, %[inc]\n"
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"\tsll %[inc], 8, %[lock]\n"
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"\tst %[lock],[%[ptr]]\n" /* Release the lock */
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: [inc] "=&r" (increment), [lock] "=r" (lock),
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[ignore] "=&r" (ignore)
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: "0" (increment), [ptr] "r" (ptr)
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);
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#else
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__asm__ __volatile__("1: ldstub [%4 + 3], %1\n"
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"\torcc %1, 0, %2\n"
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"\tbne 1b\n" /* go back until we have the lock */
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"\tld [%4], %0\n"
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"\tsra %0, 8, %0\n"
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"\tsub %0, 1, %0\n"
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"\tsll %0, 8, %1\n"
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"\tst %1,[%4]\n" /* Release the lock */
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: "=&r" (increment), "=r" (lock), "=&r" (ignore)
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: "0" (increment), "r" (ptr)
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);
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#endif
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return increment == 0;
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}
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/***** MIPS *****/
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/* This is disabled because the asm code is broken on most MIPS
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* processors and doesn't generally compile. */
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#elif defined(HAVE_CPU_MIPS) && defined(__GNUC__) && 0
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GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
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GST_INLINE_FUNC void gst_atomic_int_set (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC gint gst_atomic_int_read (GstAtomicInt *aint) { return aint->counter; }
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/* this only works on MIPS II and better */
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GST_INLINE_FUNC void
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gst_atomic_int_add (GstAtomicInt *aint, gint val)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"1: ll %0, %1 # atomic_add\n"
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" addu %0, %2 \n"
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" sc %0, %1 \n"
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" beqz %0, 1b \n"
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: "=&r" (temp), "=m" (aint->counter)
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: "Ir" (val), "m" (aint->counter));
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}
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GST_INLINE_FUNC void
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gst_atomic_int_inc (GstAtomicInt *aint)
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{
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gst_atomic_int_add (aint, 1);
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}
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GST_INLINE_FUNC gboolean
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gst_atomic_int_dec_and_test (GstAtomicInt *aint)
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{
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unsigned long temp, result;
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int val = 1;
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__asm__ __volatile__(
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".set push \n"
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".set noreorder # atomic_sub_return\n"
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"1: ll %1, %2 \n"
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" subu %0, %1, %3 \n"
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" sc %0, %2 \n"
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" beqz %0, 1b \n"
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" subu %0, %1, %3 \n"
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".set pop \n"
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: "=&r" (result), "=&r" (temp), "=m" (aint->counter)
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: "Ir" (val), "m" (aint->counter)
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: "memory");
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return result == 0;
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}
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/***** S/390 *****/
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#elif defined(HAVE_CPU_S390) && defined(__GNUC__)
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typedef struct { volatile int counter; } atomic_t __attribute__ ((aligned (4)));
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GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
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GST_INLINE_FUNC void gst_atomic_int_set (GstAtomicInt *aint, gint val) { aint->counter = val; }
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GST_INLINE_FUNC gint gst_atomic_int_read (GstAtomicInt *aint) { return aint->counter; }
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#define __CS_LOOP(old_val, new_val, ptr, op_val, op_string) \
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__asm__ __volatile__(" l %0,0(%3)\n" \
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"0: lr %1,%0\n" \
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op_string " %1,%4\n" \
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" cs %0,%1,0(%3)\n" \
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" jl 0b" \
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: "=&d" (old_val), "=&d" (new_val), \
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"+m" (((atomic_t *)(ptr))->counter) \
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: "a" (ptr), "d" (op_val) : "cc" );
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GST_INLINE_FUNC void
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gst_atomic_int_add (GstAtomicInt *aint, gint val)
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{
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int old_val, new_val;
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__CS_LOOP(old_val, new_val, aint, val, "ar");
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}
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GST_INLINE_FUNC void
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gst_atomic_int_inc (GstAtomicInt *aint)
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{
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int old_val, new_val;
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__CS_LOOP(old_val, new_val, aint, 1, "ar");
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}
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GST_INLINE_FUNC gboolean
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gst_atomic_int_dec_and_test (GstAtomicInt *aint)
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{
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int old_val, new_val;
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__CS_LOOP(old_val, new_val, aint, 1, "sr");
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return new_val == 0;
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}
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#else
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/* no need warning about this if we can't do inline assembly */
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#ifdef __GNUC__
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#warning consider putting your architecture specific atomic implementations here
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#endif
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/*
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* generic implementation
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*/
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GST_INLINE_FUNC void
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gst_atomic_int_init (GstAtomicInt *aint, gint val)
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{
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aint->counter = val;
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aint->lock = g_mutex_new ();
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}
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GST_INLINE_FUNC void
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gst_atomic_int_destroy (GstAtomicInt *aint)
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{
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g_mutex_free (aint->lock);
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}
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GST_INLINE_FUNC void
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gst_atomic_int_set (GstAtomicInt *aint, gint val)
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{
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g_mutex_lock (aint->lock);
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aint->counter = val;
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g_mutex_unlock (aint->lock);
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}
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GST_INLINE_FUNC gint
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gst_atomic_int_read (GstAtomicInt *aint)
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{
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gint res;
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g_mutex_lock (aint->lock);
|
|
res = aint->counter;
|
|
g_mutex_unlock (aint->lock);
|
|
|
|
return res;
|
|
}
|
|
|
|
GST_INLINE_FUNC void
|
|
gst_atomic_int_add (GstAtomicInt *aint, gint val)
|
|
{
|
|
g_mutex_lock (aint->lock);
|
|
aint->counter += val;
|
|
g_mutex_unlock (aint->lock);
|
|
}
|
|
|
|
GST_INLINE_FUNC void
|
|
gst_atomic_int_inc (GstAtomicInt *aint)
|
|
{
|
|
g_mutex_lock (aint->lock);
|
|
aint->counter++;
|
|
g_mutex_unlock (aint->lock);
|
|
}
|
|
|
|
GST_INLINE_FUNC gboolean
|
|
gst_atomic_int_dec_and_test (GstAtomicInt *aint)
|
|
{
|
|
gboolean res;
|
|
|
|
g_mutex_lock (aint->lock);
|
|
aint->counter--;
|
|
res = (aint->counter == 0);
|
|
g_mutex_unlock (aint->lock);
|
|
|
|
return res;
|
|
}
|
|
|
|
#endif
|
|
/*
|
|
* common functions
|
|
*/
|
|
GST_INLINE_FUNC GstAtomicInt*
|
|
gst_atomic_int_new (gint val)
|
|
{
|
|
GstAtomicInt *aint;
|
|
|
|
aint = g_new0 (GstAtomicInt, 1);
|
|
gst_atomic_int_init (aint, val);
|
|
|
|
return aint;
|
|
}
|
|
|
|
GST_INLINE_FUNC void
|
|
gst_atomic_int_free (GstAtomicInt *aint)
|
|
{
|
|
gst_atomic_int_destroy (aint);
|
|
g_free (aint);
|
|
}
|
|
|
|
#endif /* defined (GST_CAN_INLINE) || defined (__GST_TRASH_STACK_C__)*/
|
|
|
|
G_END_DECLS
|
|
|
|
#endif /* __GST_ATOMIC_IMPL_H__ */
|