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gstconfig.h.in: initial RISC-V support

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RISC-V supports unaligned accesses, but these might run extremely slowly
depending on the implementation. Therefore set GST_HAVE_UNALIGNED_ACCESS
to 0 on this architecture.

https://bugzilla.gnome.org/show_bug.cgi?id=795271
This commit is contained in:
Aurelien Jarno 2018-04-15 00:49:55 +02:00 committed by Sebastian Dröge
parent 4456792218
commit 8a156d1725
1 changed files with 1 additions and 1 deletions
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2
gst/gstconfig.h.in
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@ -104,7 +104,7 @@
* http://docs.oracle.com/cd/E19205-01/820-4155/c++_faq.html#Vers6
* https://software.intel.com/en-us/node/583402
*/
#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__)
#if defined(__alpha__) || defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__bfin) || defined(__hppa__) || defined(__nios2__) || defined(__MICROBLAZE__) || defined(__mips__) || defined(__or1k__) || defined(__sh__) || defined(__SH4__) || defined(__sparc__) || defined(__sparc) || defined(__ia64__) || defined(_M_ALPHA) || defined(_M_ARM) || defined(_M_IA64) || defined(__xtensa__) || defined(__e2k__) || defined(__riscv)
# define GST_HAVE_UNALIGNED_ACCESS 0
#elif defined(__i386__) || defined(__i386) || defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__ppc__) || defined(__ppc64__) || defined(__powerpc__) || defined(__powerpc64__) || defined(__m68k__) || defined(_M_IX86) || defined(_M_AMD64) || defined(_M_X64) || defined(__s390__) || defined(__s390x__) || defined(__zarch__)
# define GST_HAVE_UNALIGNED_ACCESS 1