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Hide GCC assembly behind define(__GNUC__). From Brian Cameron.

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Original commit message from CVS:
Hide GCC assembly behind define(__GNUC__).  From Brian Cameron.
This commit is contained in:
David Schleef 2003-01-21 22:11:13 +00:00
parent ba1f005623
commit 7106505492
2 changed files with 14 additions and 14 deletions
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16
gst/gstarch.h
View file

@ -30,7 +30,7 @@
/***** Intel x86 *****/
#if defined(HAVE_CPU_I386)
#if defined(HAVE_CPU_I386) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__( "movl %0, %%esp\n" : : "r"(stackpointer) );
@ -43,7 +43,7 @@
/***** PowerPC *****/
#elif defined (HAVE_CPU_PPC)
#elif defined (HAVE_CPU_PPC) && defined(__GNUC__)
/* should bring this in line with others and use an "r" */
#define GST_ARCH_SET_SP(stackpointer) \
@ -68,7 +68,7 @@ struct minimal_ppc_stackframe {
/***** DEC[/Compaq/HP?/Intel?] Alpha *****/
#elif defined(HAVE_CPU_ALPHA)
#elif defined(HAVE_CPU_ALPHA) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("bis $31,%0,$30" : : "r"(stackpointer));
@ -94,7 +94,7 @@ struct minimal_stackframe {
/***** ARM *****/
#elif defined(HAVE_CPU_ARM)
#elif defined(HAVE_CPU_ARM) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__( "mov sp, %0" : : "r"(stackpointer));
@ -110,7 +110,7 @@ struct minimal_stackframe {
/***** Sun SPARC *****/
#elif defined(HAVE_CPU_SPARC)
#elif defined(HAVE_CPU_SPARC) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__( "ta 3\n\t" \
@ -131,7 +131,7 @@ struct minimal_stackframe {
/***** MIPS *****/
#elif defined(HAVE_CPU_MIPS)
#elif defined(HAVE_CPU_MIPS) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("lw $sp,0(%0)\n\t" : : "r"(stackpointer));
@ -146,7 +146,7 @@ struct minimal_stackframe {
/***** HP-PA *****/
#elif defined(HAVE_CPU_HPPA)
#elif defined(HAVE_CPU_HPPA) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("copy %0,%%sp\n\t" : : "r"(stackpointer));
@ -160,7 +160,7 @@ struct minimal_stackframe {
#define GST_ARCH_SETUP_STACK(sp) sp -= 4
/***** S/390 *****/
#elif defined(HAVE_CPU_S390)
#elif defined(HAVE_CPU_S390) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("lr 15,%0" : : "r"(stackpointer))

12
gst/gstatomic_impl.h
View file

@ -33,7 +33,7 @@ G_BEGIN_DECLS
#if defined (GST_CAN_INLINE) || defined (__GST_ATOMIC_C__)
/***** Intel x86 *****/
#if defined (HAVE_CPU_I386)
#if defined (HAVE_CPU_I386) && defined(__GNUC__)
#ifdef GST_CONFIG_NO_SMP
#define SMP_LOCK ""
@ -78,7 +78,7 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
}
/***** PowerPC *****/
#elif defined (HAVE_CPU_PPC)
#elif defined (HAVE_CPU_PPC) && defined(__GNUC__)
#ifdef GST_CONFIG_NO_SMP
#define SMP_SYNC ""
@ -154,7 +154,7 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
}
/***** DEC[/Compaq/HP?/Intel?] Alpha *****/
#elif defined(HAVE_CPU_ALPHA)
#elif defined(HAVE_CPU_ALPHA) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
@ -206,7 +206,7 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
}
/***** Sun SPARC *****/
#elif defined(HAVE_CPU_SPARC)
#elif defined(HAVE_CPU_SPARC) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
@ -285,7 +285,7 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
}
/***** MIPS *****/
#elif defined(HAVE_CPU_MIPS)
#elif defined(HAVE_CPU_MIPS) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
@ -336,7 +336,7 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
}
/***** S/390 *****/
#elif defined(HAVE_CPU_S390)
#elif defined(HAVE_CPU_S390) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }