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Fix powerpc asm for non-gas assemblers (fixes #122952)

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Original commit message from CVS:
Fix powerpc asm for non-gas assemblers (fixes #122952)
This commit is contained in:
David Schleef 2003-09-22 21:45:52 +00:00
parent 1af7c7f579
commit 5ef86caf3c
2 changed files with 18 additions and 18 deletions
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6
gst/gstarch.h
View file

@ -47,11 +47,11 @@
/* should bring this in line with others and use an "r" */
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("lwz 1,%0" : : "m"(stackpointer))
__asm__("lwz %%r1,%0" : : "m"(stackpointer))
#define GST_ARCH_CALL(target) \
__asm__( "mr 0,%0\n\t" \
"mtlr 0\n\t" \
__asm__( "mr %%r0,%0\n\t" \
"mtlr %%r0\n\t" \
"blrl" : : "r"(target) );
struct minimal_ppc_stackframe {

30
gst/gstatomic_impl.h
View file

@ -84,15 +84,15 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
#define SMP_SYNC ""
#define SMP_ISYNC
#else
#define SMP_SYNC "sync"
#define SMP_ISYNC "\n\tisync"
#define SMP_SYNC "\tsync\n"
#define SMP_ISYNC "\tisync\n"
#endif
/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
* The old ATOMIC_SYNC_FIX covered some but not all of this.
*/
#ifdef GST_CONFIG_IBM405_ERR77
#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
#define PPC405_ERR77(ra,rb) "\tdcbt " #ra "," #rb "\n"
#else
#define PPC405_ERR77(ra,rb)
#endif
@ -108,11 +108,11 @@ gst_atomic_int_add (GstAtomicInt *aint, gint val)
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%3 # atomic_add\n\
add %0,%2,%0\n"
"1: lwarx %0,0,%3\n"
" add %0,%2,%0\n"
PPC405_ERR77(0,%3)
" stwcx. %0,0,%3 \n\
bne- 1b"
" stwcx. %0,0,%3 \n"
" bne- 1b\n"
: "=&r" (t), "=m" (aint->counter)
: "r" (val), "r" (&aint->counter), "m" (aint->counter)
: "cc");
@ -124,11 +124,11 @@ gst_atomic_int_inc (GstAtomicInt *aint)
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%2 # atomic_inc\n\
addic %0,%0,1\n"
"1: lwarx %0,0,%2\n"
" addic %0,%0,1\n"
PPC405_ERR77(0,%2)
" stwcx. %0,0,%2 \n\
bne- 1b"
" stwcx. %0,0,%2\n"
" bne- 1b\n"
: "=&r" (t), "=m" (aint->counter)
: "r" (&aint->counter), "m" (aint->counter)
: "cc");
@ -140,11 +140,11 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%1 # atomic_dec_return\n\
addic %0,%0,-1\n"
"1: lwarx %0,0,%1\n"
" addic %0,%0,-1\n"
PPC405_ERR77(0,%1)
" stwcx. %0,0,%1\n\
bne- 1b"
" stwcx. %0,0,%1\n"
" bne- 1b\n"
SMP_ISYNC
: "=&r" (t)
: "r" (&aint->counter)