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volume: Fix unit test failure for the controlled processing functions

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Going over integer arithmetic will lead to minimal rounding errors,
leading to +/-1 changes for volume==1.0. Implement the controlled
processing with floating point arithmetic, which was already done
for the C versions anyway.
This commit is contained in:
Sebastian Dröge 2010-10-08 11:49:09 +02:00
parent 7c423ba429
commit 4a0d435053
2 changed files with 40 additions and 70 deletions
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2
gst/volume/gstvolume.c
View file

@ -780,8 +780,6 @@ volume_process_controlled_int8_clamp (GstVolume * self, gpointer bytes,
orc_process_controlled_int8_1ch (data, volume, num_samples); orc_process_controlled_int8_1ch (data, volume, num_samples);
} else if (channels == 2) { } else if (channels == 2) {
orc_process_controlled_int8_2ch (data, volume, num_samples); orc_process_controlled_int8_2ch (data, volume, num_samples);
} else if (channels == 4) {
orc_process_controlled_int8_4ch (data, volume, num_samples);
} else { } else {
for (i = 0; i < num_samples; i++) { for (i = 0; i < num_samples; i++) {
vol = *volume++; vol = *volume++;

108
gst/volume/gstvolumeorc.orc
View file

@ -112,97 +112,69 @@ x2 mulf d1, d1, t2
.dest 4 d1 gint32 .dest 4 d1 gint32
.source 8 s1 gdouble .source 8 s1 gdouble
.temp 8 t1 .temp 8 t1
.temp 4 t2
muld t1, s1, 0x41E0000000000000L convld t1, d1
convdl t2, t1 muld t1, t1, s1
mulslq t1, d1, t2 convdl d1, t1
addq t1, t1, 0x0FFFFFFFL
shrsq t1, t1, 31
convql d1, t1
.function orc_process_controlled_int16_1ch .function orc_process_controlled_int16_1ch
.dest 2 d1 gint16 .dest 2 d1 gint16
.source 8 s1 gdouble .source 8 s1 gdouble
.temp 8 t1 .temp 4 t1
.temp 4 t2 .temp 4 t2
.temp 2 t3
muld t1, s1, 0x40E0000000000000L convswl t1, d1
convdl t2, t1 convlf t1, t1
convssslw t3, t2 convdf t2, s1
mulswl t2, t3, d1 mulf t1, t1, t2
addl t2, t2, 0x0FFF convfl t1, t1
shrsl t2, t2, 15 convssslw d1, t1
convlw d1, t2
.function orc_process_controlled_int16_2ch .function orc_process_controlled_int16_2ch
.dest 4 d1 gint16 .dest 4 d1 gint16
.source 8 s1 gdouble .source 8 s1 gdouble
.temp 8 t1 .temp 8 t1
.temp 4 t2 .temp 4 t2
.temp 2 t3 .temp 8 t3
muld t1, s1, 0x40E0000000000000L x2 convswl t1, d1
convdl t2, t1 x2 convlf t1, t1
convssslw t3, t2 convdf t2, s1
mergewl t2, t3, t3 mergelq t3, t2, t2
x2 mulswl t1, t2, d1 x2 mulf t3, t3, t1
x2 addl t1, t1, 0x0FFF x2 convfl t3, t3
x2 shrsl t1, t1, 15 x2 convssslw d1, t3
x2 convlw d1, t1
.function orc_process_controlled_int8_1ch .function orc_process_controlled_int8_1ch
.dest 1 d1 gint8 .dest 1 d1 gint8
.source 8 s1 gdouble .source 8 s1 gdouble
.temp 8 t1 .temp 2 t1
.temp 4 t2 .temp 4 t2
.temp 2 t3 .temp 4 t3
.temp 1 t4
muld t1, s1, 0x4060000000000000L convsbw t1, d1
convdl t2, t1 convswl t2, t1
convlw t3, t2 convlf t2, t2
convssswb t4, t3 convdf t3, s1
mulsbw t3, t4, d1 mulf t2, t2, t3
addw t3, t3, 0x0F convfl t2, t2
shrsw t3, t3, 7 convlw t1, t2
convwb d1, t3 convssswb d1, t1
.function orc_process_controlled_int8_2ch .function orc_process_controlled_int8_2ch
.dest 2 d1 gint8 .dest 2 d1 gint8
.source 8 s1 gdouble .source 8 s1 gdouble
.temp 8 t1 .temp 4 t1
.temp 4 t2 .temp 8 t2
.temp 2 t3 .temp 8 t3
.temp 1 t4
muld t1, s1, 0x4060000000000000L x2 convsbw t1, d1
convdl t2, t1 x2 convswl t2, t1
convlw t3, t2 x2 convlf t2, t2
convssswb t4, t3 convdf t1, s1
mergebw t3, t4, t4 mergelq t3, t1, t1
x2 mulsbw t2, t3, d1 x2 mulf t2, t2, t3
x2 addw t2, t2, 0x0F x2 convfl t2, t2
x2 shrsw t2, t2, 7 x2 convlw t1, t2
x2 convwb d1, t2 x2 convssswb d1, t1
.function orc_process_controlled_int8_4ch
.dest 4 d1 gint8
.source 8 s1 gdouble
.temp 8 t1
.temp 4 t2
.temp 2 t3
.temp 1 t4
muld t1, s1, 0x4060000000000000L
convdl t2, t1
convlw t3, t2
convssswb t4, t3
mergebw t3, t4, t4
mergewl t2, t3, t3
x4 mulsbw t1, t2, d1
x4 addw t1, t1, 0x0F
x4 shrsw t1, t1, 7
x4 convwb d1, t1