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fix sparc atomic functions.

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Original commit message from CVS:
Patch from James A Morrison <ja2morri@student.math.uwaterloo.ca> to
fix sparc atomic functions.
This commit is contained in:
James A Morrison 2003-05-12 23:20:55 +00:00 committed by David Schleef
parent e76153d66f
commit 34e5211a15
1 changed files with 29 additions and 23 deletions
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52
gst/gstatomic_impl.h
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@ -1,5 +1,5 @@
/* GStreamer /* GStreamer
* Copyright (C) <1999> Erik Walthinsen <omega@cse.ogi.edu> * Copyright (C) 1999, 2003 Erik Walthinsen <omega@cse.ogi.edu>
* *
* This library is free software; you can redistribute it and/or * This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Library General Public * modify it under the terms of the GNU Library General Public
@ -211,7 +211,7 @@ gst_atomic_int_dec_and_test (GstAtomicInt *aint)
} }
/***** Sun SPARC *****/ /***** Sun SPARC *****/
#elif defined(HAVE_CPU_SPARC) && defined(__GNUC__) && 0 #elif defined(HAVE_CPU_SPARC) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { } GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
@ -248,19 +248,22 @@ gst_atomic_int_read (GstAtomicInt *aint)
GST_INLINE_FUNC void GST_INLINE_FUNC void
gst_atomic_int_add (GstAtomicInt *aint, gint val) gst_atomic_int_add (GstAtomicInt *aint, gint val)
{ {
register volatile int *ptr asm ("g1"); volatile int increment, *ptr;
register int increment asm ("g2"); char lock;
ptr = &aint->counter; ptr = &(aint->counter);
increment = val;
__asm__ __volatile__( __asm__ __volatile__("1: ldstub [%[ptr] + 3], %[lock]\n"
"mov %%o7, %%g4\n\t" "\torcc %[lock], 0, %%g0\n"
"call ___atomic_add\n\t" "\tbne 1b\n" /* go back until we have the lock */
" add %%o7, 8, %%o7\n" "\tld [%[ptr]], %[inc]\n"
: "=&r" (increment) "\tsra %[inc], 8, %[inc]\n"
: "0" (increment), "r" (ptr) "\tadd %[inc], %[val], %[inc]\n"
: "g3", "g4", "g7", "memory", "cc"); "\tsll %[inc], 8, %[lock]\n"
"\tst %[lock],[%[ptr]]\n" /* Release the lock */
: [inc] "=&r" (increment), [lock] "=r" (lock)
: "0" (increment), [ptr] "r" (ptr), [val] "r" (val)
);
} }
GST_INLINE_FUNC void GST_INLINE_FUNC void
@ -272,19 +275,22 @@ gst_atomic_int_inc (GstAtomicInt *aint)
GST_INLINE_FUNC gboolean GST_INLINE_FUNC gboolean
gst_atomic_int_dec_and_test (GstAtomicInt *aint) gst_atomic_int_dec_and_test (GstAtomicInt *aint)
{ {
register volatile int *ptr asm ("g1"); volatile int increment, *ptr;
register int increment asm ("g2"); char lock;
ptr = &aint->counter; ptr = &aint->counter;
increment = 1;
__asm__ __volatile__( __asm__ __volatile__("1: ldstub [%[ptr] + 3], %[lock]\n"
"mov %%o7, %%g4\n\t" "\torcc %[lock], 0, %%g0\n"
"call ___atomic_sub\n\t" "\tbne 1b\n" /* go back until we have the lock */
" add %%o7, 8, %%o7\n" "\tld [%[ptr]], %[inc]\n"
: "=&r" (increment) "\tsra %[inc], 8, %[inc]\n"
: "0" (increment), "r" (ptr) "\tsub %[inc], 1, %[inc]\n"
: "g3", "g4", "g7", "memory", "cc"); "\tsll %[inc], 8, %[lock]\n"
"\tst %[lock],[%[ptr]]\n" /* Release the lock */
: [inc] "=&r" (increment), [lock] "=r" (lock)
: "0" (increment), [ptr] "r" (ptr)
);
return increment == 0; return increment == 0;
} }