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Added general MMX macros.
Original commit message from CVS: Added general MMX macros.
This commit is contained in:
Wim Taymans
parent
0032727103
commit
2ced491ef1
1 changed files with 725 additions and 0 deletions
725
include/mmx.h
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725
include/mmx.h
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/* mmx.h
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MultiMedia eXtensions GCC interface library for IA32.
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To use this library, simply include this header file
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and compile with GCC. You MUST have inlining enabled
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in order for mmx_ok() to work; this can be done by
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simply using -O on the GCC command line.
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Compiling with -DMMX_TRACE will cause detailed trace
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output to be sent to stderr for each mmx operation.
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This adds lots of code, and obviously slows execution to
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a crawl, but can be very useful for debugging.
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THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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AND FITNESS FOR ANY PARTICULAR PURPOSE.
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1997-98 by H. Dietz and R. Fisher
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History:
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97-98* R.Fisher Early versions
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980501 R.Fisher Original Release
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980611* H.Dietz Rewrite, correctly implementing inlines, and
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R.Fisher including direct register accesses.
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980616 R.Fisher Release of 980611 as 980616.
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980714 R.Fisher Minor corrections to Makefile, etc.
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980715 R.Fisher mmx_ok() now prevents optimizer from using
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clobbered values.
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mmx_ok() now checks if cpuid instruction is
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available before trying to use it.
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980726* R.Fisher mm_support() searches for AMD 3DNow, Cyrix
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Extended MMX, and standard MMX. It returns a
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value which is positive if any of these are
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supported, and can be masked with constants to
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see which. mmx_ok() is now a call to this
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980726* R.Fisher Added i2r support for shift functions
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980919 R.Fisher Fixed AMD extended feature recognition bug.
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980921 R.Fisher Added definition/check for _MMX_H.
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Added "float s[2]" to mmx_t for use with
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3DNow and EMMX. So same mmx_t can be used.
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981013 R.Fisher Fixed cpuid function 1 bug (looked at wrong reg)
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Fixed psllq_i2r error in mmxtest.c
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* Unreleased (internal or interim) versions
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Notes:
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It appears that the latest gas has the pand problem fixed, therefore
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I'll undefine BROKEN_PAND by default.
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String compares may be quicker than the multiple test/jumps in vendor
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test sequence in mmx_ok(), but I'm not concerned with that right now.
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Acknowledgments:
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Jussi Laako for pointing out the errors ultimately found to be
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connected to the failure to notify the optimizer of clobbered values.
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Roger Hardiman for reminding us that CPUID isn't everywhere, and that
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someone may actually try to use this on a machine without CPUID.
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Also for suggesting code for checking this.
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Robert Dale for pointing out the AMD recognition bug.
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Jimmy Mayfield and Carl Witty for pointing out the Intel recognition
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bug.
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Carl Witty for pointing out the psllq_i2r test bug.
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*/
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#ifndef _MMX_H
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#define _MMX_H
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//#define MMX_TRACE
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/* Warning: at this writing, the version of GAS packaged
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with most Linux distributions does not handle the
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parallel AND operation mnemonic correctly. If the
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symbol BROKEN_PAND is defined, a slower alternative
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coding will be used. If execution of mmxtest results
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in an illegal instruction fault, define this symbol.
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*/
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#undef BROKEN_PAND
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/* The type of an value that fits in an MMX register
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(note that long long constant values MUST be suffixed
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by LL and unsigned long long values by ULL, lest
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they be truncated by the compiler)
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*/
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typedef union {
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long long q; /* Quadword (64-bit) value */
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unsigned long long uq; /* Unsigned Quadword */
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int d[2]; /* 2 Doubleword (32-bit) values */
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unsigned int ud[2]; /* 2 Unsigned Doubleword */
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short w[4]; /* 4 Word (16-bit) values */
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unsigned short uw[4]; /* 4 Unsigned Word */
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char b[8]; /* 8 Byte (8-bit) values */
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unsigned char ub[8]; /* 8 Unsigned Byte */
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float s[2]; /* Single-precision (32-bit) value */
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} mmx_t;
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/* Function to test if multimedia instructions are supported...
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*/
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inline extern int
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mm_support(void)
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{
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/* Returns 1 if MMX instructions are supported,
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3 if Cyrix MMX and Extended MMX instructions are supported
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5 if AMD MMX and 3DNow! instructions are supported
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0 if hardware does not support any of these
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*/
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register int rval = 0;
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__asm__ __volatile__ (
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/* See if CPUID instruction is supported ... */
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/* ... Get copies of EFLAGS into eax and ecx */
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"pushf\n\t"
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"popl %%eax\n\t"
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"movl %%eax, %%ecx\n\t"
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/* ... Toggle the ID bit in one copy and store */
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/* to the EFLAGS reg */
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"xorl $0x200000, %%eax\n\t"
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"push %%eax\n\t"
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"popf\n\t"
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/* ... Get the (hopefully modified) EFLAGS */
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"pushf\n\t"
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"popl %%eax\n\t"
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/* ... Compare and test result */
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"xorl %%eax, %%ecx\n\t"
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"testl $0x200000, %%ecx\n\t"
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"jz NotSupported1\n\t" /* Nothing supported */
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/* Get standard CPUID information, and
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go to a specific vendor section */
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"movl $0, %%eax\n\t"
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"cpuid\n\t"
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/* Check for Intel */
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"cmpl $0x756e6547, %%ebx\n\t"
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"jne TryAMD\n\t"
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"cmpl $0x49656e69, %%edx\n\t"
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"jne TryAMD\n\t"
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"cmpl $0x6c65746e, %%ecx\n"
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"jne TryAMD\n\t"
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"jmp Intel\n\t"
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/* Check for AMD */
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"\nTryAMD:\n\t"
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"cmpl $0x68747541, %%ebx\n\t"
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"jne TryCyrix\n\t"
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"cmpl $0x69746e65, %%edx\n\t"
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"jne TryCyrix\n\t"
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"cmpl $0x444d4163, %%ecx\n"
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"jne TryCyrix\n\t"
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"jmp AMD\n\t"
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/* Check for Cyrix */
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"\nTryCyrix:\n\t"
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"cmpl $0x69727943, %%ebx\n\t"
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"jne NotSupported2\n\t"
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"cmpl $0x736e4978, %%edx\n\t"
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"jne NotSupported3\n\t"
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"cmpl $0x64616574, %%ecx\n\t"
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"jne NotSupported4\n\t"
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/* Drop through to Cyrix... */
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/* Cyrix Section */
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/* See if extended CPUID is supported */
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"movl $0x80000000, %%eax\n\t"
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"cpuid\n\t"
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"cmpl $0x80000000, %%eax\n\t"
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"jl MMXtest\n\t" /* Try standard CPUID instead */
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/* Extended CPUID supported, so get extended features */
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"movl $0x80000001, %%eax\n\t"
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"cpuid\n\t"
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"testl $0x00800000, %%eax\n\t" /* Test for MMX */
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"jz NotSupported5\n\t" /* MMX not supported */
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"testl $0x01000000, %%eax\n\t" /* Test for Ext'd MMX */
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"jnz EMMXSupported\n\t"
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"movl $1, %0:\n\n\t" /* MMX Supported */
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"jmp Return\n\n"
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"EMMXSupported:\n\t"
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"movl $3, %0:\n\n\t" /* EMMX and MMX Supported */
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"jmp Return\n\t"
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/* AMD Section */
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"AMD:\n\t"
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/* See if extended CPUID is supported */
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"movl $0x80000000, %%eax\n\t"
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"cpuid\n\t"
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"cmpl $0x80000000, %%eax\n\t"
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"jl MMXtest\n\t" /* Try standard CPUID instead */
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/* Extended CPUID supported, so get extended features */
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"movl $0x80000001, %%eax\n\t"
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"cpuid\n\t"
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"testl $0x00800000, %%edx\n\t" /* Test for MMX */
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"jz NotSupported6\n\t" /* MMX not supported */
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"testl $0x80000000, %%edx\n\t" /* Test for 3DNow! */
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"jnz ThreeDNowSupported\n\t"
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"movl $1, %0:\n\n\t" /* MMX Supported */
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"jmp Return\n\n"
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"ThreeDNowSupported:\n\t"
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"movl $5, %0:\n\n\t" /* 3DNow! and MMX Supported */
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"jmp Return\n\t"
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/* Intel Section */
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"Intel:\n\t"
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/* Check for MMX */
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"MMXtest:\n\t"
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"movl $1, %%eax\n\t"
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"cpuid\n\t"
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"testl $0x00800000, %%edx\n\t" /* Test for MMX */
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"jz NotSupported7\n\t" /* MMX Not supported */
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"movl $1, %0:\n\n\t" /* MMX Supported */
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"jmp Return\n\t"
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/* Nothing supported */
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"\nNotSupported1:\n\t"
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"#movl $101, %0:\n\n\t"
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"\nNotSupported2:\n\t"
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"#movl $102, %0:\n\n\t"
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"\nNotSupported3:\n\t"
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"#movl $103, %0:\n\n\t"
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"\nNotSupported4:\n\t"
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"#movl $104, %0:\n\n\t"
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"\nNotSupported5:\n\t"
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"#movl $105, %0:\n\n\t"
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"\nNotSupported6:\n\t"
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"#movl $106, %0:\n\n\t"
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"\nNotSupported7:\n\t"
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"#movl $107, %0:\n\n\t"
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"movl $0, %0:\n\n\t"
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"Return:\n\t"
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: "=a" (rval)
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: /* no input */
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: "eax", "ebx", "ecx", "edx"
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);
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/* Return */
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return(rval);
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}
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/* Function to test if mmx instructions are supported...
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*/
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inline extern int
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mmx_ok(void)
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{
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/* Returns 1 if MMX instructions are supported, 0 otherwise */
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return ( mm_support() & 0x1 );
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}
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/* Helper functions for the instruction macros that follow...
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(note that memory-to-register, m2r, instructions are nearly
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as efficient as register-to-register, r2r, instructions;
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however, memory-to-memory instructions are really simulated
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as a convenience, and are only 1/3 as efficient)
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*/
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#ifdef MMX_TRACE
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/* Include the stuff for printing a trace to stderr...
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*/
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#include <stdio.h>
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#define mmx_i2r(op, imm, reg) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (imm); \
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fprintf(stderr, #op "_i2r(" #imm "=0x%016llx, ", mmx_trace.q); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (imm)); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
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}
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#define mmx_m2r(op, mem, reg) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mem); \
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fprintf(stderr, #op "_m2r(" #mem "=0x%016llx, ", mmx_trace.q); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "X" (mem)); \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
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}
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#define mmx_r2m(op, reg, mem) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #reg ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2m(" #reg "=0x%016llx, ", mmx_trace.q); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=X" (mem) \
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: /* nothing */ ); \
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mmx_trace = (mem); \
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fprintf(stderr, #mem "=0x%016llx\n", mmx_trace.q); \
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}
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#define mmx_r2r(op, regs, regd) \
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{ \
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mmx_t mmx_trace; \
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__asm__ __volatile__ ("movq %%" #regs ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #op "_r2r(" #regs "=0x%016llx, ", mmx_trace.q); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%016llx) => ", mmx_trace.q); \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd); \
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__asm__ __volatile__ ("movq %%" #regd ", %0" \
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: "=X" (mmx_trace) \
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: /* nothing */ ); \
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fprintf(stderr, #regd "=0x%016llx\n", mmx_trace.q); \
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}
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#define mmx_m2m(op, mems, memd) \
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{ \
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mmx_t mmx_trace; \
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mmx_trace = (mems); \
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fprintf(stderr, #op "_m2m(" #mems "=0x%016llx, ", mmx_trace.q); \
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mmx_trace = (memd); \
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||||||
|
fprintf(stderr, #memd "=0x%016llx) => ", mmx_trace.q); \
|
||||||
|
__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
|
||||||
|
#op " %1, %%mm0\n\t" \
|
||||||
|
"movq %%mm0, %0" \
|
||||||
|
: "=X" (memd) \
|
||||||
|
: "X" (mems)); \
|
||||||
|
mmx_trace = (memd); \
|
||||||
|
fprintf(stderr, #memd "=0x%016llx\n", mmx_trace.q); \
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
/* These macros are a lot simpler without the tracing...
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define mmx_i2r(op, imm, reg) \
|
||||||
|
__asm__ __volatile__ (#op " $" #imm ", %%" #reg \
|
||||||
|
: /* nothing */ \
|
||||||
|
: /* nothing */);
|
||||||
|
|
||||||
|
#define mmx_m2r(op, mem, reg) \
|
||||||
|
__asm__ __volatile__ (#op " %0, %%" #reg \
|
||||||
|
: /* nothing */ \
|
||||||
|
: "X" (mem))
|
||||||
|
|
||||||
|
#define mmx_r2m(op, reg, mem) \
|
||||||
|
__asm__ __volatile__ (#op " %%" #reg ", %0" \
|
||||||
|
: "=X" (mem) \
|
||||||
|
: /* nothing */ )
|
||||||
|
|
||||||
|
#define mmx_r2r(op, regs, regd) \
|
||||||
|
__asm__ __volatile__ (#op " %" #regs ", %" #regd)
|
||||||
|
|
||||||
|
#define mmx_m2m(op, mems, memd) \
|
||||||
|
__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
|
||||||
|
#op " %1, %%mm0\n\t" \
|
||||||
|
"movq %%mm0, %0" \
|
||||||
|
: "=X" (memd) \
|
||||||
|
: "X" (mems))
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x64 MOVe Quadword
|
||||||
|
(this is both a load and a store...
|
||||||
|
in fact, it is the only way to store)
|
||||||
|
*/
|
||||||
|
#define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
|
||||||
|
#define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
|
||||||
|
#define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
|
||||||
|
#define movq(vars, vard) \
|
||||||
|
__asm__ __volatile__ ("movq %1, %%mm0\n\t" \
|
||||||
|
"movq %%mm0, %0" \
|
||||||
|
: "=X" (vard) \
|
||||||
|
: "X" (vars))
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x32 MOVe Doubleword
|
||||||
|
(like movq, this is both load and store...
|
||||||
|
but is most useful for moving things between
|
||||||
|
mmx registers and ordinary registers)
|
||||||
|
*/
|
||||||
|
#define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
|
||||||
|
#define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
|
||||||
|
#define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
|
||||||
|
#define movd(vars, vard) \
|
||||||
|
__asm__ __volatile__ ("movd %1, %%mm0\n\t" \
|
||||||
|
"movd %%mm0, %0" \
|
||||||
|
: "=X" (vard) \
|
||||||
|
: "X" (vars))
|
||||||
|
|
||||||
|
|
||||||
|
/* 2x32, 4x16, and 8x8 Parallel ADDs
|
||||||
|
*/
|
||||||
|
#define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
|
||||||
|
#define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
|
||||||
|
#define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
|
||||||
|
|
||||||
|
#define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
|
||||||
|
#define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
|
||||||
|
#define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
|
||||||
|
|
||||||
|
#define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
|
||||||
|
#define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
|
||||||
|
#define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
|
||||||
|
*/
|
||||||
|
#define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
|
||||||
|
#define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
|
||||||
|
#define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
|
||||||
|
|
||||||
|
#define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
|
||||||
|
#define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
|
||||||
|
#define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
|
||||||
|
*/
|
||||||
|
#define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
|
||||||
|
#define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
|
||||||
|
#define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
|
||||||
|
|
||||||
|
#define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
|
||||||
|
#define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
|
||||||
|
#define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 2x32, 4x16, and 8x8 Parallel SUBs
|
||||||
|
*/
|
||||||
|
#define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
|
||||||
|
#define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
|
||||||
|
#define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
|
||||||
|
|
||||||
|
#define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
|
||||||
|
#define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
|
||||||
|
#define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
|
||||||
|
|
||||||
|
#define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
|
||||||
|
#define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
|
||||||
|
#define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
|
||||||
|
*/
|
||||||
|
#define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
|
||||||
|
#define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
|
||||||
|
#define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
|
||||||
|
|
||||||
|
#define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
|
||||||
|
#define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
|
||||||
|
#define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
|
||||||
|
*/
|
||||||
|
#define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
|
||||||
|
#define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
|
||||||
|
#define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
|
||||||
|
|
||||||
|
#define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
|
||||||
|
#define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
|
||||||
|
#define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 4x16 Parallel MULs giving Low 4x16 portions of results
|
||||||
|
*/
|
||||||
|
#define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
|
||||||
|
#define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
|
||||||
|
#define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 4x16 Parallel MULs giving High 4x16 portions of results
|
||||||
|
*/
|
||||||
|
#define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
|
||||||
|
#define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
|
||||||
|
#define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 4x16->2x32 Parallel Mul-ADD
|
||||||
|
(muls like pmullw, then adds adjacent 16-bit fields
|
||||||
|
in the multiply result to make the final 2x32 result)
|
||||||
|
*/
|
||||||
|
#define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
|
||||||
|
#define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
|
||||||
|
#define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x64 bitwise AND
|
||||||
|
*/
|
||||||
|
#ifdef BROKEN_PAND
|
||||||
|
#define pand_m2r(var, reg) \
|
||||||
|
{ \
|
||||||
|
mmx_m2r(pandn, (mmx_t) -1LL, reg); \
|
||||||
|
mmx_m2r(pandn, var, reg); \
|
||||||
|
}
|
||||||
|
#define pand_r2r(regs, regd) \
|
||||||
|
{ \
|
||||||
|
mmx_m2r(pandn, (mmx_t) -1LL, regd); \
|
||||||
|
mmx_r2r(pandn, regs, regd) \
|
||||||
|
}
|
||||||
|
#define pand(vars, vard) \
|
||||||
|
{ \
|
||||||
|
movq_m2r(vard, mm0); \
|
||||||
|
mmx_m2r(pandn, (mmx_t) -1LL, mm0); \
|
||||||
|
mmx_m2r(pandn, vars, mm0); \
|
||||||
|
movq_r2m(mm0, vard); \
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
#define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
|
||||||
|
#define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
|
||||||
|
#define pand(vars, vard) mmx_m2m(pand, vars, vard)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x64 bitwise AND with Not the destination
|
||||||
|
*/
|
||||||
|
#define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
|
||||||
|
#define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
|
||||||
|
#define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x64 bitwise OR
|
||||||
|
*/
|
||||||
|
#define por_m2r(var, reg) mmx_m2r(por, var, reg)
|
||||||
|
#define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
|
||||||
|
#define por(vars, vard) mmx_m2m(por, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x64 bitwise eXclusive OR
|
||||||
|
*/
|
||||||
|
#define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
|
||||||
|
#define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
|
||||||
|
#define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
|
||||||
|
(resulting fields are either 0 or -1)
|
||||||
|
*/
|
||||||
|
#define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
|
||||||
|
#define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
|
||||||
|
#define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
|
||||||
|
|
||||||
|
#define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
|
||||||
|
#define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
|
||||||
|
#define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
|
||||||
|
|
||||||
|
#define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
|
||||||
|
#define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
|
||||||
|
#define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
|
||||||
|
(resulting fields are either 0 or -1)
|
||||||
|
*/
|
||||||
|
#define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
|
||||||
|
#define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
|
||||||
|
#define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
|
||||||
|
|
||||||
|
#define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
|
||||||
|
#define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
|
||||||
|
#define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
|
||||||
|
|
||||||
|
#define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
|
||||||
|
#define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
|
||||||
|
#define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
|
||||||
|
*/
|
||||||
|
#define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
|
||||||
|
#define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
|
||||||
|
#define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
|
||||||
|
#define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
|
||||||
|
|
||||||
|
#define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg)
|
||||||
|
#define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
|
||||||
|
#define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
|
||||||
|
#define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
|
||||||
|
|
||||||
|
#define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg)
|
||||||
|
#define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
|
||||||
|
#define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
|
||||||
|
#define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
|
||||||
|
*/
|
||||||
|
#define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg)
|
||||||
|
#define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
|
||||||
|
#define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
|
||||||
|
#define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
|
||||||
|
|
||||||
|
#define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg)
|
||||||
|
#define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
|
||||||
|
#define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
|
||||||
|
#define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
|
||||||
|
|
||||||
|
#define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg)
|
||||||
|
#define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
|
||||||
|
#define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
|
||||||
|
#define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 2x32 and 4x16 Parallel Shift Right Arithmetic
|
||||||
|
*/
|
||||||
|
#define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg)
|
||||||
|
#define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
|
||||||
|
#define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
|
||||||
|
#define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
|
||||||
|
|
||||||
|
#define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg)
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#define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
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#define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
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#define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
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|
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|
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/* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
|
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|
(packs source and dest fields into dest in that order)
|
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|
*/
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#define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
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#define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
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|
#define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
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|
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#define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
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#define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
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|
#define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
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|
|
||||||
|
|
||||||
|
/* 4x16->8x8 PACK and Unsigned Saturate
|
||||||
|
(packs source and dest fields into dest in that order)
|
||||||
|
*/
|
||||||
|
#define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
|
||||||
|
#define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
|
||||||
|
#define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
|
||||||
|
(interleaves low half of dest with low half of source
|
||||||
|
as padding in each result field)
|
||||||
|
*/
|
||||||
|
#define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
|
||||||
|
#define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
|
||||||
|
#define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
|
||||||
|
|
||||||
|
#define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
|
||||||
|
#define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
|
||||||
|
#define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
|
||||||
|
|
||||||
|
#define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
|
||||||
|
#define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
|
||||||
|
#define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
|
||||||
|
(interleaves high half of dest with high half of source
|
||||||
|
as padding in each result field)
|
||||||
|
*/
|
||||||
|
#define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
|
||||||
|
#define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
|
||||||
|
#define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
|
||||||
|
|
||||||
|
#define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
|
||||||
|
#define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
|
||||||
|
#define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
|
||||||
|
|
||||||
|
#define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
|
||||||
|
#define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
|
||||||
|
#define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
|
||||||
|
|
||||||
|
|
||||||
|
/* Empty MMx State
|
||||||
|
(used to clean-up when going from mmx to float use
|
||||||
|
of the registers that are shared by both; note that
|
||||||
|
there is no float-to-mmx operation needed, because
|
||||||
|
only the float tag word info is corruptible)
|
||||||
|
*/
|
||||||
|
#ifdef MMX_TRACE
|
||||||
|
|
||||||
|
#define emms() \
|
||||||
|
{ \
|
||||||
|
fprintf(stderr, "emms()\n"); \
|
||||||
|
__asm__ __volatile__ ("emms"); \
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
#define emms() __asm__ __volatile__ ("emms")
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
Loading…
Reference in a new issue