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Merge pull request #133 from ferrous-systems/rtic-up
adapt to breaking changes in cortex-m-rtic 0.5.x
This commit is contained in:
commit
9296ff5b09
1 changed files with 17 additions and 7 deletions
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@ -10,7 +10,7 @@ use core::{
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time::Duration,
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};
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use cortex_m::asm;
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use cortex_m::{asm, peripheral::NVIC};
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use embedded_hal::digital::v2::{OutputPin as _, StatefulOutputPin};
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#[cfg(feature = "beginner")]
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pub use hal::ieee802154;
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@ -176,10 +176,7 @@ impl ops::DerefMut for Timer {
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///
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/// This return an `Err`or if called more than once
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pub fn init() -> Result<Board, ()> {
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if let (Some(mut core), Some(periph)) = (
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cortex_m::Peripherals::take(),
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hal::target::Peripherals::take(),
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) {
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if let Some(periph) = hal::target::Peripherals::take() {
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// NOTE(static mut) this branch runs at most once
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#[cfg(feature = "advanced")]
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static mut EP0IN_BUF: [u8; 64] = [0; 64];
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@ -216,8 +213,21 @@ pub fn init() -> Result<Board, ()> {
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log::debug!("Clocks configured");
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let mut rtc = Rtc::new(periph.RTC0);
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rtc.enable_interrupt(RtcInterrupt::Overflow, Some(&mut core.NVIC));
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rtc.enable_interrupt(RtcInterrupt::Overflow, None);
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rtc.enable_counter();
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// NOTE(unsafe) because this crate defines the `#[interrupt] fn RTC0` interrupt handler,
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// RTIC cannot manage that interrupt (trying to do so results in a linker error). Thus it
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// is the task of this crate to mask/unmask the interrupt in a safe manner.
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//
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// Because the RTC0 interrupt handler does *not* access static variables through a critical
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// section (that disables interrupts) this `unmask` operation cannot break critical sections
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// and thus won't lead to undefined behavior (e.g. torn reads/writes)
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//
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// the preceding `enable_conuter` method consumes the `rtc` value. This is a semantic move
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// of the RTC0 peripheral from this function (which can only be called at most once) to the
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// interrupt handler (where the peripheral is accessed without any synchronization
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// mechanism)
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unsafe { NVIC::unmask(Interrupt::RTC0) };
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log::debug!("RTC started");
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@ -291,7 +301,7 @@ impl Log for Logger {
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// Counter of OVERFLOW events -- an OVERFLOW occurs every (1<<24) ticks
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static OVERFLOWS: AtomicU32 = AtomicU32::new(0);
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// NOTE this will at the highest priority, higher priority than RTIC tasks
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// NOTE this will run at the highest priority, higher priority than RTIC tasks
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#[interrupt]
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fn RTC0() {
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let curr = OVERFLOWS.load(Ordering::Relaxed);
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